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R8C/20 Group, R8C/21 Group 19. Flash Memory

Rev.2.00 Aug 27, 2008 Page 398 of 458

REJ09B0250-0200

19.4.5 Full Status Check

When an error occurs, the FMR06 to FMR07 bits in the FMR0 register are set to 1, indicating occurrence of

each specific error. Therefore, checking these status bits (full status check) can determine the executed result.

Table 19.6 lists the Errors and FMR0 Register Status. Figure 19.16 shows the Full Status Check and Handling

Procedure for Individual Errors.

NOTE:

1. The MCU enters read array mode by writing FFh in the second bus cycle of these commands, at the

same time the command code written in the first bus cycle will disabled.

Table 19.6 Errors and FMR0 Register Status

FMR0 Register (Status

Error Error Occurrence Condition

FMR07(SR5) FMR06(SR4)

1 1 Command

sequence

error

• When any command is not written correctly

• When invalid data other than those that can be written

in the second bus cycle of the block erase command is

written (i.e., other than D0h or FFh)

(1)

• When executing the program command or block erase

command while rewriting is disabled using the FMR02

bit in the FMR0 register, the FMR15 or FMR16 bit in the

FMR1 register.

• When inputting and erasing the address in which the

Flash memory is not allocated during the erase

command input

• When executing to erase the block which disables

rewriting during the erase command input.

• When inputting and writing the address in which the

Flash memory is not allocated during the write

command input.

• When executing to write the block which disables

rewriting during the write command input.

1 0 Erase error • When the block erase command is executed but not

automatically erased correctly

0 1 Program error • When the program command is executed but not

automatically programmed correctly.

Renesas R8C/20 User Manual

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