R8C/20 Group, R8C/21 Group 19. Flash Memory
Rev.2.00 Aug 27, 2008 Page 382 of 458
REJ09B0250-0200
19.4 CPU Rewrite Mode
In CPU rewrite mode, user ROM area can be rewritten by executing software commands from the CPU. Therefore,
the user ROM area can be rewritten directly while the MCU is mounted on a board without using such as a ROM
programmer. Execute the program and block erase commands only to each block in user ROM area.
When an interrupt request is generated during an erase operation in CPU rewrite mode, the flash module contains
an erase-suspend function which performs the interrupt process after the erase operation is halted temporarily.
During the erase-suspend, user ROM area can be read by a program.
When an interrupt request is generated during the auto-program operation in CPU rewrite mode, the flash module
contains a program-suspend function which performs the interrupt process after the auto-program operation
suspends. During the program-suspend, user ROM area can be read by a program.
CPU rewrite mode contains erase write 0 mode (EW0 mode) and erase write 1 mode (EW1 mode).
Table 19.3 lists the Differences between EW0 Mode and EW1 Mode.
NOTE:
1. When setting the FMR02 bit in the FMR0 register to 1 (rewrite enables) and rewriting block 0 is enabled by
setting the FMR15 bit in the FMR1 register to 0 (rewrite enables). Rewriting block 1 is enabled by setting the
FMR16 bit to 0 (rewrite enables).
Table 19.3 Differences between EW0 Mode and EW1 Mode
Item EW0 Mode EW1 Mode
Operating Mode Single chip mode Single chip mode
Areas in which a Rewrite
Control Program Can be
Located
User ROM area User ROM area
Areas in which a Rewrite
Control Program can be
Executed
Necessary to transfer to any areas
other than the flash memory (e.g.,
RAM) before executing
Executing directly in user ROM or RAM
area possible
Areas which can be
Rewritten
User ROM area User ROM area
However, other than the blocks
which contain a rewrite control
program
(1)
Software Command
Restriction
None •
Program and block erase commands
Cannot be run on any block which
contains a rewrite control program
• Read status register command
Cannot be executed
Modes After Program or
Erase
Read status register mode Read array mode
Modes After Read Status
Register
Read status register mode Do not execute this command
CPU Status During Auto-
write and Auto-erase
Operating Hold state (I/O ports hold state
before the command is executed)
Flash Memory Status
Detection
• Read the FMR00, FMR06, and
FMR07 bits in the FMR0 register by
a program
• Execute the read status register
command and read the SR7, SR5,
and SR4 bits in the status register.
Read the FMR00, FMR06, and
FMR07 bits in the FMR0 register by a
program
Conditions for Transition to
Erase-suspend
Set the FMR40 and FMR41 bits in
the FMR4 register to 1 by a program.
The FMR40 bit in the FMR4 register
is set to 1 and the interrupt request of
the enabled maskable interrupt is
generated
Conditions for Transitions to
Program-suspend
Set the FMR40 and FMR42 bits in the
FMR4 register to 1 by a program.
The FMR40 bit in the FMR4 register is
set to 1 and the interrupt request of the
enabled maskable interrupt is generated
CPU Clock 5 MHz or below No restriction to the following (clock
frequency to be used)
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