R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface
Rev.2.00 Aug 27, 2008 Page 310 of 458
REJ09B0250-0200
16.2.7 SCS Pin Control and Arbitration
When setting the SSUMS bit in the SSMR2 register to 1 (4-wire bus communication mode), and the CSS1 bit in
the SSMR2 register to 1 (functions as SCS
output pin), Set the MSS bit in the SSCRH register to 1 (operates as
a master device) and check the arbitration of the SCS
pin before starting serial transfer. If the clock synchronous
serial I/O with chip select detects that the synchronized internal SCS
signal is held “L” in this period, the CE bit
in the SSSR register to 1 (a conflict error occurs) and the MSS bit is automatically set to 0 (operates as a slave
device).
Figure 16.21 shows an Arbitration Check Timing.
A future transmit operation is not performed while the CE bit is set to 1. Set the CE bit to 0 (a conflict error does
not occur) before a transmit is started.
Figure 16.21 Arbitration Check Timing
Data write to
SSTDR register
Maximum time of SCS internal
synchronization
During arbitration detection
High-impedance
SCS input
Internal SCS
(synchronization)
MSS bit in
SSCRH register
Transfer start
CE
SCS output
0
1
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