R8C/20 Group, R8C/21 Group 13. Watchdog Timer
Rev.2.00 Aug 27, 2008 Page 117 of 458
REJ09B0250-0200
13.2 Count Source Protection Mode Enabled
The count source of the watchdog timer is the low-speed on-chip oscillator clock when count source protection
mode is enabled. If the CPU clock stops when the program is out of control, the clock can be supplied to the
watchdog timer.
Table 13.3 lists the Watchdog Timer Specifications (with Count Source Protection Mode Enabled).
NOTES:
1. The WDTON bit cannot be changed by a program. When setting the WDTON bit, write 0 to the bit 0
of the address 0FFFFh using a flash programmer.
2. Even if writing 0 to the CSPROINI bit in the OFS register, the CSPRO bit is set to 1. The CSPROINI
bit cannot be changed by a program. When setting the CSPROINI bit, write 0 to the bit 7 of the
address 0FFFFh using a flash programmer.
Table 13.3 Watchdog Timer Specifications (with Count Source Protection Mode Enabled)
Item Specification
Count Source Low-speed on-chip oscillator clock
Count Operation Decrement
Period Count value of watchdog timer (4096)
Low-speed on-chip oscillator clock
e.g. Period is approximately 32.8 ms when the low-speed on-chip
oscillator clock is 125 kHz
Count Start Condition
The WDTON bit
(1)
in the OFS register (0FFFFh) selects the operation
of the watchdog timer after reset.
• When the WDTON bit is set to 1 (watchdog timer is in stop state
after reset)
The watchdog timer and prescaler stop after reset and the count
starts by writing to the WDTS register
• When the WDTON bit is set to 0 (watchdog timer starts
automatically after reset)
The watchdog timer and prescaler start counting automatically after
reset
Reset Condition of Watchdog
Timer
• Reset
• Write 00h to the WDTR register before writing FFh
• Underflow
Count Stop Condition None (the count does not stop in wait mode after the count starts. The
MCU does not enter stop mode)
Operation at the Time of
Underflow
Watchdog timer reset (refer to 5.5 Watchdog Timer Reset)
Register, Bit • When setting the CSPPRO bit in the CSPR register to 1 (count
source protection mode is enabled)
(2)
, the following are set
automatically
- Set 0FFFh to the watchdog timer
- Set the CM14 bit in the CM1 register to 0 (low-speed on-chip
oscillator on)
- Set the PM12 bit in the PM1 register to 1 (The watchdog timer is
reset when watchdog timer underflows)
• The following states are held in count source protection mode
- Writing to the CM10 bit in the CM1 register disables (It remains
unchanged even if it is set to 1. The MCU does not enter stop
mode)
- Writing to the CM14 bit in the CM1 register disables (It remains
unchanged even if it is set to 1. The low-speed on-chip oscillator
does not stop)
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