R8C/20 Group, R8C/21 Group 13. Watchdog Timer
Rev.2.00 Aug 27, 2008 Page 113 of 458
REJ09B0250-0200
13. Watchdog Timer
The watchdog timer is a function to detect when the program is out of control. To use the watchdog timer is
recommend for improving reliability of a system. The watchdog timer contains a 15-bit counter and can select count
source protection mode is enabled or disabled.
Table 13.1 lists the Count Source Protection Mode
Refer to 5.5 Watchdog Timer Reset for details of the watchdog timer reset.
Figure 13.1 shows the Block Diagram of Watchdog Timer, Figure 13.2 shows Registers OFS and WDC and Figure
13.3 shows Registers WDTR, WDTS, and CSPR.
Figure 13.1 Block Diagram of Watchdog Timer
Table 13.1 Count Source Protection Mode
Item
Count Source Protection
Mode Disabled
Count Source Protection
Mode Enabled
Count Source CPU clock Low-speed on-chip oscillator
clock
Count Operation Decrement
Count Start Condition Either of following can be selected
• After reset, count starts automatically
• Count starts by writing to WDTS register
Count Stop Condition Stop mode, wait mode None
Reset Condition of Watchdog
Timer
• Reset
• Write 00h to the WDTR register before writing FFh
• Underflow
Operation at the Time of
Underflow
Watchdog timer interrupt or
watchdog timer reset
Watchdog timer reset
CPU clock
1/16
1/128
Watchdog timer
Internal reset signal
(“L” active)
Write to WDTR register
WDC7 = 0
WDC7 = 1
Set to
7FFFh
(1)
PM12 = 1
Watchdog
timer reset
PM12 = 0
Watchdog timer
interrupt request
Prescaler
CSPRO = 0
fOCO-S
CSPRO = 1
CSPRO: Bit in CSPR register
WDC7: Bit in WDC register
PM12: Bit in PM1 register
NOTE:
1. When the CSPRO bit is set to 1 (count source protection mode enabled), 0FFFh is set.
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