R8C/20 Group, R8C/21 Group 19. Flash Memory
Rev.2.00 Aug 27, 2008 Page 405 of 458
REJ09B0250-0200
19.7 Notes on Flash Memory
19.7.1 CPU Rewrite Mode
19.7.1.1 Operating Speed
Before entering CPU rewrite mode (EW0 mode), select 5 MHz or below for the CPU clock using the CM06 bit
in the CM0 register and the CM16 to CM17 bits in the CM1 register. This usage note is not needed for EW1
mode.
19.7.1.2 Prohibited Instructions
The following instructions cannot be used in EW0 mode because the flash memory internal data is referenced:
UND, INTO, and BRK instructions.
19.7.1.3 Interrupts
Table 19.9 lists the EW0 Mode Interrupts and Table 19.10 lists the EW1 Mode Interrupts.
NOTES:
1. Do not use the address match interrupt while the command is executed because the vector of the
address match interrupt is allocated on ROM.
2. Do not use the non-maskable interrupt while block 0 is automatically erased because the fixed
vector is allocated block 0.
Table 19.9 EW0 Mode Interrupts
Mode Status
When Maskable Interrupt
Request is
Acknowledged
When Watchdog Timer, Oscillation Stop
Detection and Voltage Monitor 2 Interrupt
Request are Acknowledged
EW0 During automatic erasing Any interrupt can be used
by allocating a vector to
RAM
Once an interrupt request is acknowledged,
the auto-programming or auto-erasing is
forcibly stopped immediately and resets the
flash memory. An interrupt process starts
after the fixed period and the flash memory
restarts. Since the block during the auto-
erasing or the address during the auto-
programming is forcibly stopped, the
normal value may not be read. Execute the
auto-erasing again and ensure the auto-
erasing is completed normally.
Since the watchdog timer does not stop
during the command operation, the
interrupt request may be generated. Reset
the watchdog timer regularly.
Automatic writing
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