R8C/20 Group, R8C/21 Group 21. Usage Notes
Rev.2.00 Aug 27, 2008 Page 431 of 458
REJ09B0250-0200
21.2.5 Changing Interrupt Control Register Contents
(a) Each interrupt control register can only be changed while interrupt requests corresponding to that
register are not generated. If interrupt requests may be generated, disable the interrupts before changing
the interrupt control register.
(b) When changing any interrupt control register after disabling interrupts, be careful with the instructions
to be used.
When changing any bit other than IR bit
If an interrupt request corresponding to that register is generated while executing the instruction, the IR
bit may not be set to 1 (interrupt requested), and the interrupt request may be ignored. If this causes a
problem, use the following instructions to change the register.
Instructions to use: AND, OR, BCLR, BSET
When changing IR bit
If the IR bit is set to 0 (interrupt not requested), it may not be set to 0 depending on the instruction to be
used. Therefore, use the MOV instruction to set the IR bit to 0.
(c) When disabling interrupts using the I flag, set the I flag according to the following sample programs.
Refer to (b) for the change of interrupt control registers in the sample programs.
Sample programs 1 to 3 are preventing the I flag from being set to 1 (interrupt enables) before changing the
interrupt control register for reasons of the internal bus or the instruction queue buffer.
Example 1: Use NOP instructions to prevent I flag being set to 1 before interrupt control register is
changed
INT_SWITCH1:
FCLR I ; Disable interrupts
AND.B #00H,0056H ; Set TRAIC register to 00h
NOP ;
NOP
FSET I ; Enable interrupts
Example 2: Use dummy read to have FSET instruction wait
INT_SWITCH2:
FCLR I ; Disable interrupts
AND.B #00H,0056H ; Set TRAIC register to 00h
MOV.W MEM,R0 ; Dummy read
FSET I ; Enable interrupts
Example 3: Use POPC instruction to change I flag
INT_SWITCH3:
PUSHC FLG
FCLR I ; Disable interrupts
AND.B #00H,0056H ; Set TRAIC register to 00h
POPC FLG ; Enable interrupts