R8C/20 Group, R8C/21 Group 10. Clock Generation Circuit
Rev.2.00 Aug 27, 2008 Page 68 of 458
REJ09B0250-0200
Figure 10.4 OCD Register
Oscillation Stop Detection Register
(1)
Symbol Address After Reset
OCD
000Ch 00000100b
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3.
4.
5.
6.
7.
b7 b6 b5 b4 b3 b2 b1 b0
0000
OCD1 RW
OCD0 RW
Oscillation stop detection enable
bit
(7)
0 : Oscillation stop detection function
disabled
(2)
1 : Oscillation stop detection function enabled
0 : Disable
(2)
1 : Enable
Oscillation stop detection
interrupt enable bit
OCD2
System clock select bit
(4)
0 : Selects XIN clock
(7)
1 : Selects on-chip oscillator clock
(3)
RW
OCD3
Clock monitor bit
(5,6)
0 : XIN clock oscillates
1 : XIN clock stops
RO
—
(b7-b4)
Reserved bits Set to 0
RW
The OCD3 bit remains 0 (XIN clock oscillates) if the OCD1 to OCD0 bits are set to 00b.
The CM14 bit is set to 0 (low -speed on-chip oscillator on) if the OCD2 bit is set to 1 (selects on-chip oscillator clock).
Refer to
Figure 10.13 Procedure for Switching Clock Source from Low-Speed On-Chip Oscillator to XIN
Clock
for the sw itching procedure w hen the XIN clock re-oscillates after detecting an oscillation stop.
Set the PRC0 bit in the PRCR register to 1 (enables w riting) before rew riting to the OCD register.
The OCD2 bit is automatically set to 1 (selects on-chip oscillator clock) if a XIN clock oscillation stop is detected w hile
the OCD1 to OCD0 bits are set to 11b. If the OCD3 bit is set to 1 (XIN clock stops), the OCD2 bit remains unchanged
w hen w riting 0 (selects XIN clock).
The OCD3 bit is enabled when the OCD0 bit is set to 1 (oscillation stop detection function enabled).
Set the OCD1 to OCD0 bits to 00b before entering stop and high-speed on-chip oscillator mode, low -speed on-chip
oscillator mode (XIN clock stops). Set the OCD1 to OCD0 bits to 00b w hen the FRA01 bit in the FRA0 register is set to
1 (selects high-speed on-chip oscillator).
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