RL78/G13 CHAPTER 6 TIMER ARRAY UNIT
R01UH0146EJ0100 Rev.1.00 362
Sep 22, 2011
6.5 Operation Timing of Counter
6.5.1 Count clock (f
TCLK)
The count clock (f
TCLK) of the timer array unit can be selected between following by CCSmn bit of timer mode register
mn (TMRmn). .
• Operation clock (f
MCK) specified by the CKSmn0 and CKSmn1 bits
• Valid edge of input signal input from the TImn pin
Because the timer array unit is designed to operate in synchronization with f
CLK, the timings of the count clock (fTCLK) are
shown below.
(1) When operation clock (f
MCK) specified by the CKSmn0 and CKSmn1 bits is selected (CCSmn = 0)
The count clock (fTCLK) is between fCLK to fCLK /2
15
by setting of timer clock select register m (TPSm). When a
divided f
CLK is selected, however, the count clock is not a signal which is simply divided fCLK by 2
m
, but a signal
which becomes high level for one period of f
CLK from its rising edge (m = 1 to 15).
Counting of timer count register mn (TCRmn) delayed by one period of fCLK from rising edge of the count clock,
because of synchronization with f
CLK. But, this is described as “counting at rising edge of the count clock”, as a
matter of convenience.
Figure 6-21. Timing of f
CLK and count clock (fTCLK) (When CCSmn = 0)
Remarks 1. : Rising edge of the count clock
: Synchronization, increment/decrement of counter
2. f
CLK: CPU/peripheral hardware clock
fCLK
f
TCLK
( = f
MCK
= CKmn)
fCLK/2
fCLK/4
fCLK/8
fCLK/16
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