EasyManuals Logo
Home>Renesas>Computer Hardware>RL78/G13

Renesas RL78/G13 User Manual

Renesas RL78/G13
1092 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Page #490 background imageLoading...
Page #490 background image
RL78/G13 CHAPTER 10 WATCHDOG TIMER
R01UH0146EJ0100 Rev.1.00 471
Sep 22, 2011
10.4 Operation of Watchdog Timer
10.4.1 Controlling operation of watchdog timer
1. When the watchdog timer is used, its operation is specified by the option byte (000C0H).
Enable counting operation of the watchdog timer by setting bit 4 (WDTON) of the option byte (000C0H) to 1 (the
counter starts operating after a reset release) (for details, see CHAPTER 24).
WDTON Watchdog Timer Counter
0 Counter operation disabled (counting stopped after reset)
1 Counter operation enabled (counting started after reset)
Set an overflow time by using bits 3 to 1 (WDCS2 to WDCS0) of the option byte (000C0H) (for details, see 10.4.2
and CHAPTER 24).
Set a window open period by using bits 6 and 5 (WINDOW1 and WINDOW0) of the option byte (000C0H) (for
details, see 10.4.3 and CHAPTER 24).
2. After a reset release, the watchdog timer starts counting.
3. By writing “ACH” to the watchdog timer enable register (WDTE) after the watchdog timer starts counting and before
the overflow time set by the option byte, the watchdog timer is cleared and starts counting again.
4. After that, write the WDTE register the second time or later after a reset release during the window open period. If
the WDTE register is written during a window close period, an internal reset signal is generated.
5. If the overflow time expires without “ACH” written to the WDTE register, an internal reset signal is generated.
An internal reset signal is generated in the following cases.
If a 1-bit manipulation instruction is executed on the WDTE register
If data other than “ACH” is written to the WDTE register
Cautions 1. When data is written to the watchdog timer enable register (WDTE) for the first time after reset
release, the watchdog timer is cleared in any timing regardless of the window open time, as long
as the register is written before the overflow time, and the watchdog timer starts counting again.
2. If the watchdog timer is cleared by writing “ACH” to the WDTE register, the actual overflow time
may be different from the overflow time set by the option byte by up to 2/f
IL seconds.
3. The watchdog timer can be cleared immediately before the count value overflows.

Table of Contents

Other manuals for Renesas RL78/G13

Questions and Answers:

Renesas RL78/G13 Specifications

General IconGeneral
BrandRenesas
ModelRL78/G13
CategoryComputer Hardware
LanguageEnglish

Related product manuals