RL78/G13 CHAPTER 24 OPTION BYTE
R01UH0146EJ0100 Rev.1.00 923
Sep 22, 2011
24.2 Format of User Option Byte
The format of user option byte is shown below.
Figure 24-1. Format of User Option Byte (000C0H/010C0H)
Address: 000C0H/010C0H
Note 1
7 6 5 4 3 2 1 0
WDTINIT WINDOW1 WINDOW0 WDTON WDCS2 WDCS1 WDCS0 WDSTBYON
WDTINIT Use of interval interrupt of watchdog timer
0 Interval interrupt is not used.
1 Interval interrupt is generated when 75% of the overflow time is reached.
WINDOW1 WINDOW0 Watchdog timer window open period
Note 2
0 0 Setting prohibited
0 1 50%
1 0 75%
1 1 100%
WDTON Operation control of watchdog timer counter
0 Counter operation disabled (counting stopped after reset)
1 Counter operation enabled (counting started after reset)
WDCS2 WDCS1 WDCS0 Watchdog timer overflow time
(f
IL = 17.25 kHz (MAX.))
0 0 0 2
6
/fIL (3.71 ms)
0 0 1 2
7
/fIL (7.42 ms)
0 1 0 2
8
/fIL (14.84 ms)
0 1 1 2
9
/fIL (29.68 ms)
1 0 0 2
11
/fIL (118.72 ms)
1 0 1 2
13
/fIL (474.90 ms)
1 1 0 2
14
/fIL (949.80 ms)
1 1 1 2
16
/fIL (3799.19m s)
WDSTBYON Operation control of watchdog timer counter (HALT/STOP mode)
0 Counter operation stopped in HALT/STOP mode
Note 2
1 Counter operation enabled in HALT/STOP mode
Notes 1. Set the same value as 000C0H to 010C0H when the boot swap operation is used because 000C0H is
replaced by 010C0H.
2. The window open period is 100% when WDSTBYON = 0, regardless the value of the WINDOW1 and
WINDOW0 bits.
Caution The watchdog timer continues its operation during EEPROM emulation. During processing, the
interrupt acknowledge time is delayed. Set the overflow time and window size taking this delay into
consideration.
Remark f
IL: Low-speed on-chip oscillator clock frequency
<R>
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