Renesas RL78/G13 User Manual

RL78/G13 CHAPTER 27 BCD CORRECTION CIRCUIT
R01UH0146EJ0100 Rev.1.00 955
Sep 22, 2011
CHAPTER 27 BCD CORRECTION CIRCUIT
27.1 BCD Correction Circuit Function
The result of addition/subtraction of the BCD (binary-coded decimal) code and BCD code can be obtained as BCD
code with this circuit.
The decimal correction operation result is obtained by performing addition/subtraction having the A register as the
operand and then adding/ subtracting the BCD correction result register (BCDADJ).
27.2 Registers Used by BCD Correction Circuit
The BCD correction circuit uses the following registers.
• BCD correction result register (BCDADJ)
(1) BCD correction result register (BCDADJ)
The BCDADJ register stores correction values for obtaining the add/subtract result as BCD code through
add/subtract instructions using the A register as the operand.
The value read from the BCDADJ register varies depending on the value of the A register when it is read and those
of the CY and AC flags.
The BCDADJ register is read by an 8-bit memory manipulation instruction.
Reset input sets this register to undefined.
Figure 27-1. Format of BCD Correction Result Register (BCDADJ)
Address: F00FEH After reset: undefined R
Symbol 7 6 5 4 3 2 1 0
BCDADJ

Renesas RL78/G13 Specifications

General

Core	RL78
Architecture	16-bit
CPU Speed	32 MHz
Operating Voltage	1.6 V to 5.5 V
Operating Temperature	-40°C to +85°C
Low Power Consumption	Yes
Timers	Multiple 16-bit timers
ADC	10-bit
Communication Interfaces	UART, I2C
Package Options	LQFP, QFN
DMA Channels	Available
D/A Converter	No