RL78/G13 CHAPTER 19 RESET FUNCTION
R01UH0146EJ0100 Rev.1.00 869
Sep 22, 2011
CHAPTER 19 RESET FUNCTION
The following seven operations are available to generate a reset signal.
(1) External reset input via RESET pin
(2) Internal reset by watchdog timer program loop detection
(3) Internal reset by comparison of supply voltage and detection voltage of power-on-reset (POR) circuit
(4) Internal reset by comparison of supply voltage of the voltage detector (LVD) and detection voltage
(5) Internal reset by execution of illegal instruction
Note
(6) Internal reset by RAM parity error
(7) Internal reset by illegal-memory access
External and internal resets start program execution from the address at 0000H and 0001H when the reset signal is
generated.
A reset is effected when a low level is input to the RESET pin, the watchdog timer overflows, or by POR and LVD
circuit voltage detection, execution of illegal instruction
Note
, RAM parity error or illegal-memory access, and each item of
hardware is set to the status shown in Tables 19-1.
When a low level is input to the RESET pin, the device is reset. It is released from the reset status when a high level is
input to the RESET pin and program execution is started with the high-speed on-chip oscillator clock after reset
processing. A reset by the watchdog timer is automatically released, and program execution starts using the high-speed
on-chip oscillator clock (see Figures 19-2 to 19-4) after reset processing. Reset by POR and LVD circuit supply voltage
detection is automatically released when V
DD ≥ VPOR or VDD ≥ VLVI after the reset, and program execution starts using the
high-speed on-chip oscillator clock (see CHAPTER 20 POWER-ON-RESET CIRCUIT and CHAPTER 21 VOLTAGE
DETECTOR) after reset processing.
Note The illegal instruction is generated when instruction code FFH is executed.
Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip debug
emulator.
Cautions 1. For an external reset, input a low level for 10
μ
s or more to the RESET pin.
(To perform an external reset upon power application, a low level of at least 10
μ
s must be
continued during the period in which the supply voltage is within the operating range (V
DD ≥ 1.6
V).)
2. During reset input, the X1 clock, XT1 clock, high-speed on-chip oscillator clock, and low-speed
on-chip oscillator clock stop oscillating. External main system clock input and external
subsystem clock input become invalid.
3. When reset is effected, port pin P130 is set to low-level output and other port pins become high-
impedance, because each SFR and 2nd SFR are initialized.
Remark V
POR: POR power supply rise detection voltage
<R>
To Next Page
Loading...
Need help?
General
