Renesas RL78 Series User Manual

RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT
R01UH0368EJ0210 Rev.2.10 531
Dec 10, 2015
Figure 6-76. Operation Procedure When PWM Function Is Used (1/2)
Software Operation Hardware Status
TAU
default
setting
Power-off status
(Clock supply is stopped and writing to each register is
disabled.)
Sets the TAUmEN bit of peripheral enable register 0
(PER0) to 1.
Power-on status. Each channel stops operating.
(Clock supply is started and writing to each register is
enabled.)
Sets timer clock select register m (TPSm).
Determines clock frequencies of CKm0 to CKm3.
Channel
default
setting
Sets timer mode registers mn, mp (TMRmn, TMRmp) of
two channels to be used (determines operation mode of
channels).
An interval (period) value is set to timer data register mn
(TDRmn) of the master channel, and a duty factor is set
to the TDRmp register of the slave channel.
Channel stops operating.
(Clock is supplied and some power is consumed.)
Sets slave channel.
The TOMmp bit of timer output mode register m
(TOMm) is set to 1 (slave channel output mode).
Sets the TOLmp bit.
Sets the TOmp bit and determines default level of the
TOmp output.
Sets the TOEmp bit to 1 and enables operation of TOmp.
Clears the port register and port mode register to 0.
The TOmp pin goes into Hi-Z output state.
The TOmp default setting level is output when the port
mode register is in output mode and the port register is 0.
TOmp does not change because channel stops operating.
The TOmp pin outputs the TOmp set level.
(Remarks are listed on the next page.)

Renesas RL78 Series Specifications

General

Brand	Renesas
Model	RL78 Series
Category	Computer Hardware
Language	English