MB95630H Series
150 FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E
CHAPTER 11 8/16-BIT COMPOSITE TIMER
11.9 Operation of PWM Timer Function
(Fixed-cycle Mode)
11.9 Operation of PWM Timer Function
(Fixed-cycle Mode)
This section describes the operation of the PWM timer function (fixed-cycle
mode) of the 8/16-bit composite timer.
■ Operation of PWM Timer Function (Fixed-cycle Mode)
To use the PWM timer function (fixed-cycle mode), do the settings shown in Figure 11.9-1.
Figure 11.9-1 Settings for PWM Timer Function (Fixed-cycle Mode)
As for the PWM timer function (fixed-cycle mode), PWM signal that has a fixed cycle and
variable "H" pulse width is output from the timer output pin (TOn0/TOn1). The cycle is fixed
at "0xFF" in 8-bit operation or "0xFFFF" in 16-bit operation. The time is determined by the
count clock selected. The "H" pulse width is specified by the value in the 8/16-bit composite
timer data register (Tn0DR/Tn1DR).
This function has no effect on the interrupt flag (Tn0CR1/Tn1CR1:IF). Since each cycle
always starts with "H" pulse output, the timer output initial value setting bit (Tn0CR1/
Tn1CR1:SO) has no effect on operation.
The value of the 8/16-bit composite timer data register (Tn0DR/Tn1DR) is transferred to the
temporary storage latch (comparison data storage latch) in the comparator either when the
counter starts counting or when a counter value comparison match is detected.
When the timer stops operation, the timer output bit (TMCRn:TO0/TO1) holds the last value.
In the output waveform immediately after activation of the timer (write "1" to the STA bit), the
"H" pulse is one count clock shorter than the value set in the Tn0DR/Tn1DR register.
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
Tn0CR0/Tn1CR0 IFE C2 C1 C0 F3 F2 F1 F0
× ❍❍❍ 0011
Tn0CR1/Tn1CR1 STA HO IE IR BF IF SO OE
❍❍×××××❍
TMCRn TO1 TO0 TIS MOD FE11 FE10 FE01 FE00
❍❍× ❍❍❍❍❍
Tn0DR/Tn1DR Sets "H" pulse width (compare value)
❍: Bit to be used
×: Unused bit
1: Set to "1"
0: Set to "0"
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