MB95630H Series
MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED 361
CHAPTER 20 16-BIT RELOAD TIMER
20.6 Operations and Setting Procedure Example
20.6 Operations and Setting Procedure Example
This section describes the operating status of the 16-bit reload timer counter.
â– Operating Status of Counter
The counter status is determined by the value of the count enable bit (CNTE) in the 16-bit
reload timer control status register (lower) ch. n (TMCSRLn) and the internal signal start
trigger wait signal (WAIT). The STOP state (halted), WAIT state (waiting for a start trigger)
and RUN state (operating state) can be set.
Figure 20.6-1 shows the status transition of these counters.
Figure 20.6-1 Diagram of Counter State Transition
Reset
STOP state CNTE = 0, WAIT = 1
TIn pin: Input disabled
TOn pin: General-purpose I/O port
16-bit reload timer timer register ch. n:
Holds the value at stop
Value immediately after reset = 0x0000
WAIT state CNTE = 1, WAIT = 1
TIn pin: Only trigger input is valid
TOn pin: 16-bit reload timer reload register ch. n output
16-bit reload timer timer register ch. n:
Holds the value at stop
Until loaded immediately after reset = 0x0000
RUN state CNTE = 1, WAIT = 0
TIn pin: 16-bit reload timer input
TOn pin: 16-bit reload timer reload register ch. n output
16-bit reload timer timer register ch. n:
Count operation
LOAD CNTE = 1, WAIT = 0
16-bit reload timer reload register ch. n value
loaded to16-bit reload timer timer register ch. n
: State transition by hardware
: State transition by register access
: WAIT signal (internal signal)
: Software trigger bit (TMCSRLn)
: Timer operation enable bit (TMCSRLn)
: Underflow generation flag bit (TMCSRLn)
: Reload selection bit (TMCSRLn)
WAIT
TRG
CNTE
UF
RELD
CNTE = 0
CNTE = 1
TRG = 0
CNTE = 1
TRG = 1
CNTE = 0
External trigger from TOn pin
TRG = 1
(Software trigger)
Load completed
TRG = 1
(Software trigger)
UF = 1 &
RELD = 0
(One-shot mode)
UF = 1 &
RELD = 1
(Reload mode)
External trigger from TIn pin
CNTE = 0
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