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General| Brand | Fujitsu |
|---|---|
| Model | 8FX |
| Category | Computer Hardware |
| Language | English |
Describes the manual's goal, target audience, and general information about the MB95630H Series microcontrollers.
Information regarding company and brand names, which are trademarks or registered trademarks of their respective owners.
Provides information on free sample programs for peripheral resources of the New 8FX family of microcontrollers.
Explains methods for searching for function details, including CONTENTS and register searches.
Briefly describes the structure of the manual, where each chapter explains one peripheral function.
Lists and defines terminology used within the manual, such as Word and Byte definitions.
Explains notations used in the 'Register Configuration' section, covering bits, fields, attributes, and initial values.
Details the single-chip memory access mode supported by the MB95630H Series, including mode data settings.
Describes the CPU's dedicated registers, including PC, Accumulator, Temporary Accumulator, Index Register, Extra Pointer, Stack Pointer, and Program Status.
Explains the general-purpose registers, their configuration, features, and usage in interrupt handling and sub-routine calls.
Explains how 16-bit data is stored in memory, including states in RAM, specified by operands, and in the stack.
Provides a general overview of the clock controller, its functions, and supported clocks.
Details the various registers associated with the clock controller, such as SYCC, PLLC, WATR, STBC, SYCC2, and STBC2.
Describes the five available clock modes: main clock, main CR clock, main CR PLL clock, subclock, and sub-CR clock modes.
Explains the operations in low power consumption modes, including sleep, stop, time-base timer, and watch modes.
Explains the CPU's behavior during reset, including reset sources and the reset operation flow.
Details the registers related to reset operations, specifically the Reset Source Register (RSRR).
Provides important notes and considerations for using the reset functionality, including register initialization.
Provides an overview of the interrupt system, detailing interrupt request inputs, levels, and interrupt processing.
Explains the step-by-step procedure for processing interrupts, including interrupt controller actions and CPU response.
Discusses the concept of nested interrupts and how they are handled based on interrupt priority levels.
Details the time required for interrupt processing, including sampling wait time and interrupt handling time.
Provides a general overview of the I/O port functionality for controlling general-purpose I/O pins.
Details the configuration and operations of I/O ports, covering their elements and usage as input, output, or peripheral function pins.
Provides an overview of the time-base timer, its operating modes, and its interval timer function.
Details the configuration of the time-base timer, including its constituent blocks and input/output clocks.
Lists and describes the registers associated with the time-base timer, specifically the Time-base Timer Control Register (TBTC).
Provides notes and considerations for using the time-base timer, including interrupt handling and clearing mechanisms.
Provides an overview of the watch prescaler, a 16-bit down-counting free-run counter with an interval timer function.
Details the configuration of the watch prescaler, including its constituent blocks and input/output clocks.
Lists the registers associated with the watch prescaler, specifically the Watch Prescaler Control Register (WPCR).
Provides notes and considerations for using the watch prescaler, including interrupt setting and clearing.
Provides an overview of the wild register function, its purpose for patching bugs, and its components.
Details the block diagram and configuration of the wild register function, including memory area and control circuit blocks.
Explains the procedure for setting up the wild register function, including writing addresses and data.
Lists and describes the registers used for the wild register function, such as WRDR, WRAR, WREN, and WROR.
Provides an overview of the 8/16-bit composite timer, its structure, and its functions like interval, PWM, PWC, and input capture.
Details the configuration of the 8/16-bit composite timer, including its constituent blocks and registers.
Describes the types of interrupts generated by the 8/16-bit composite timer for Timer n0 and Timer n1.
Lists and describes the registers used for the 8/16-bit composite timer, covering status control, data, mode control, and buffer registers.
Provides notes on using the 8/16-bit composite timer, including considerations for function switching, data modification, and operation in standby/stop modes.
Provides an overview of the external interrupt circuit, its function of detecting edges on external pins, and generating interrupt requests.
Details the configuration of the external interrupt circuit, including its edge detection circuits and control register.
Describes the interrupt mechanism for the external interrupt circuit, focusing on edge detection and request generation.
Lists and describes the registers for the external interrupt circuit, specifically the External Interrupt Control Register (EIC).
Provides an overview of the interrupt pin selection circuit, which selects pins for interrupt input from various peripheral input pins.
Details the configuration of the interrupt pin selection circuit, including its block diagram and control register.
Lists and describes the registers for the interrupt pin selection circuit, specifically the Interrupt Pin Selection Circuit Control Register (WICR).
Provides notes on using the interrupt pin selection circuit, covering pin selection, interrupt enable, and behavior in standby mode.
Provides an overview of the LIN-UART, a general-purpose serial data communication interface for synchronous or asynchronous communication.
Details the configuration of the LIN-UART, listing its constituent blocks such as reload counter, shift registers, and control registers.
Explains how to select the LIN-UART baud rate using the dedicated baud rate generator or external clock, including calculation formulas.
Lists and describes the registers for the LIN-UART, including serial control, mode, status, data, extended status, extended communication, and baud rate generator registers.
Provides an overview of the 8/10-bit A/D converter, a 10-bit successive approximation type with selectable input signals.
Details the configuration of the 8/10-bit A/D converter, including its constituent blocks and the number of analog input pins.
Explains the operations and provides setting examples for activating the A/D conversion function via software or continuous activation.
Lists the registers for the 8/10-bit A/D converter, including control registers and data registers.
Provides an overview of the low-voltage detection reset circuit, which monitors power supply voltage and generates a reset signal.
Details the configuration of the low-voltage detection reset circuit, including its block diagram and registers.
Explains the operation of the low-voltage detection reset circuit, including reset threshold voltage and operation in standby mode.
Lists the registers for the low-voltage detection reset circuit, specifically the LVD Reset Voltage Selection ID Register (LVDR).
Provides an overview of the clock supervisor counter, its function in detecting abnormal external clock states.
Details the configuration of the clock supervisor counter, including its constituent blocks and registers.
Explains the operations of the clock supervisor counter, including different operating modes and counter behavior.
Lists the registers for the clock supervisor counter, including Clock Monitoring Data Register (CMDR) and Clock Monitoring Control Register (CMCR).
Provides an overview of the 8/16-bit PPG, an 8-bit reload timer module for pulse output control.
Details the configuration of the 8/16-bit PPG, including its block diagram and constituent blocks.
Describes the interrupts generated by the 8/16-bit PPG when a counter borrow is detected.
Lists and describes the registers for the 8/16-bit PPG, including control, cycle setup, duty setup, start, and output reverse registers.
Provides an overview of the 16-bit PPG timer, capable of PWM and one-shot output, with variable period and duty.
Details the configuration of the 16-bit PPG timer, including its blocks and registers.
Describes the interrupt generation conditions for the 16-bit PPG timer, including trigger, counter borrow, and edge detection.
Lists and describes the registers for the 16-bit PPG timer, including downcounter, cycle setting, duty setting, status control, and start registers.
Provides an overview of the 16-bit reload timer, its operating modes (reload, one-shot, event count), and its interval timer capability.
Details the configuration of the 16-bit reload timer, including its constituent blocks and registers.
Describes the interrupt generation for the 16-bit reload timer when an underflow occurs on the downcounter.
Lists and describes the registers for the 16-bit reload timer, including control status registers and timer/reload registers.
Provides an overview of the multi-pulse generator, its components (PPG timer, reload timer, waveform sequencer), and output signal control.
Presents the block diagrams for the multi-pulse generator and its waveform sequencer, illustrating component connections.
Explains the operations of the multi-pulse generator, focusing on output data registers, waveform timing, position detection, and DTTI input control.
Lists and describes the registers for the multi-pulse generator, including output control, output data buffer, input control, compare clear, timer buffer, timer control status, and noise cancellation registers.
Provides an overview of the UART/SIO, a general-purpose serial data communication interface supporting synchronous and asynchronous modes.
Details the configuration of the UART/SIO, listing its constituent blocks such as mode control registers, status registers, and data registers.
Describes the interrupt-related bits and sources for the UART/SIO, including receive and transmit interrupts.
Lists and describes the registers for the UART/SIO, including serial mode control, serial status and data, serial input data, and serial output data registers.
Provides an overview of the I2C bus interface, its two-wire bidirectional bus, and its master/slave capabilities.
Details the configuration of the I2C bus interface, listing its constituent blocks such as clock selector, registers, and control circuits.
Describes the interrupts generated by the I2C bus interface, including transfer and stop interrupts.
Lists and describes the registers for the I2C bus interface, including bus control, status, data, address, and clock control registers.
Describes the basic configuration for serial programming connection using Fujitsu Semiconductor's BGM adaptors.
Provides an example of a serial programming connection, illustrating the MCU transiting to PGM mode via timing diagrams.
Provides an overview of the dual operation Flash memory, its location, banks, and features like simultaneous read/write operations.
Details the sector and bank configuration of the dual operation Flash memory for different memory sizes.
Describes the procedures for reading/resetting, programming, chip-erasing, sector-erasing, sector erase suspend, and sector erase resume commands.
Lists the registers for the Flash memory, including status registers and sector write control registers.
Provides an overview of the NVR interface, its reserved area in Flash for system information, and its functions.
Details the configuration of the NVR interface, including blocks for clock trimming, watchdog timer selection, and temperature adjustment.
Lists the registers for the NVR interface, including CRTH, CRTL, CRTDA, WDTH, and WDTL registers.
Provides notes on using the NVR interface, including changing main CR frequency and handling flash erase and trimming values.
Provides an overview of the comparator, its function in monitoring analog input voltages, and generating interrupts on output edge changes.
Details the configuration of the comparator module, including its blocks and control register.
Describes the output edge detection interrupt generated by the comparator.
Explains how to activate the comparator using software and provides an example procedure for setting it up.
Provides an overview of the system configuration controller, its system configuration register (SYSC), and its functions.
Describes the system configuration register (SYSC), which is an 8-bit register for configuring the clock and reset system.
Provides notes on using the controller, specifically regarding the setting of PPGSEL when using the Multi-pulse Generator (MPG).
Explains the ten types of addressing methods used in F2MC-8FX instructions, including direct, extended, and bit direct addressing.
Explains special instructions such as JMP @A, MOVW A, PC, MULU A, DIVU A, and XCHW A, PC.
Describes bit manipulation instructions like SETB and CLRB, and notes on read-modify-write operations and read destinations.
Provides tables listing transfer, arithmetic operation, branch, and other instructions used in F2MC-8FX.
Shows the instruction map of F2MC-8FX, illustrating the organization of instruction codes and operands.
