JUNOS Internet Software Network Operations Guide: Hardware
374 ! Determining PCG Mastership
Step 2: Look at the PCG LEDs on the Faceplate
Action To check the PCG LEDs, look on the PCG faceplate at the rear of the M40e or M160
router chassis (see Figure 153 on page 370 and Figure 154 on page 371). Table 90
describes the PCG LED states. If the blue
MASTER LED on the PCG faceplate is on
steadily, the PCG is functioning as master.
Step 3: Display the Packet Forwarding Engine Current Clock Source
The Packet Forwarding Engine current clock source is the master PCG.
Action To display the PCG master from the Packet Forwarding Engine clock source output,
use the following CLI command:
user@host> show chassis clocks
Sample Output
user@host>
show chassis clocks
PFE clock status:
Current source PCG 0
Measured frequency 125.03 MHz
Reference clock status:
Current source Primary
Primary source Internal
Secondary source Internal
Tertiary source Internal
Rollover algorithm Holdover
PLL mode Free-running
PLL errors 0
Sync message current 0x00
Sync message normal 0x00
Sync message override 0x00
What It Means The command output shows that the PCG in slot 0 is the primary clock source.
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