Parker Hannifin
Encoder Input Mode
The ACR9000 and ACR9030 can be set to any one of six encoder modes.
The new command
ENCm SRCn has been added to support the new modes,
and is directly equivalent to setting or clearing the flags. The table below
summarizes the choices for the flags and the corresponding valid values of
“n” for SRC. These values are saved with the
ESAVE command and read
from flash on power up.
The encoder source can be changed with the following command, where m
is the encoder number and n is the mode number.
ENCm SRCn
The following example sets encoder one’s source to a quadrature encoder.
P00>ENC1 SRC0
The following table can be used for setup of the different encoder modes for
the ACR9000 and ACR9030.
SRC Input
Configuration
Channel A use Channel B use
0 Quadrature Encoder Channel A Channel B
1 Step and Direction Step Direction
2 CW/CCW steps CW step CCW step
3 SSI Encoder SCLK SDATA
- RESERVED
5 Step and Direction (Int.) Step Direction
6 CW/CCW steps (Int.) CW step CCW step
- RESERVED
Encoder Error Detection
The ACR FPGAs have a phase error detection enable bit (PEEN), which will
normally always be set, enabling detection of erroneous transitions on
channel A and B. If the error is detected, no counts are recorded for that
transition, and a latched bit in the FPGA is set to record the event. When
firmware detects that bit, it sets the “encoder signal fault” flag. In the
RES
command, the PEEN is toggled (1 to 0 to 1) to clear the latch fault bit. The
FPGAs also have a bit that reflects the state of encoder cable disconnect
detection circuitry on the boards. That bit is not latched. When firmware
detects that bit, it sets the “encoder signal lost” flag. In the
RES command,
the flag is cleared, but if the cable is still disconnected, the flag will be set
again.
The ACR9000 and ACR9030 controllers support two encoder error flags.
These are the first two bits in the encoder flags parameter, “encoder signal
fault” and “encoder signal lost.” When using the
DRIVE IO (Enable Drive I/O
=1) and an encoder error is detected, by default, the drive disables and the
Kill All Motion bit is set for the axis to which the fault encoder is attached.
Both bits are cleared by the
RES or ENC RES, or DRIVE command. If an
encoder error is detected, the controller will cease reading the encoder until
the error is cleared. This default response to an encoder error can be
inhibited by setting the Disable Encoder Fault Response flag, bit index 3 in
the Drive Control flags.
Appendix D Drive I/O 123
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