RL78/G10 CHAPTER 6 TIMER ARRAY UNIT
R01UH0384EJ0311 Rev. 3.11 138
Dec 22, 2016
6.4.2 Basic rules of 8-bit timer operation function (only channels 1 and 3)
The 8-bit timer operation function makes it possible to use a 16-bit timer channel in a configuration consisting of two 8-
bit timer channels.
This function can only be used for channels 1 and 3, and there are several rules for using it.
The basic rules for this function are as follows:
(1) The 8-bit timer operation function applies only to channels 1 and 3.
(2) When using 8-bit timers, set the SPLIT bit of timer mode register 0nH (TMR0nH) to 1.
(3) The higher 8 bits can be operated as the interval timer function.
(4) At the start of operation, the higher 8 bits output the interrupt request signal (INTTM01H, INTTM03H) (which is the
same operation performed when MD0n0 is set to 1).
(5) The operation clock of the higher 8 bits is selected according to the CKS0n1 bit of the lower-bit TMR0nH register.
(6) For the higher 8 bits, the TSH0n bit is manipulated to start channel operation and the TTH0n bit is manipulated to
stop channel operation. The channel status can be checked using the TEH0n bit.
(7) The lower 8 bits operate according to the settings of TMR0nH and TMR0nL registers. The lower 8-bit timer
supports the following functions:
• Interval timer
• Square wave output
• External event counter
• Delay counter
• PWM output function
• Multiple PWM output function (16-pin products only)
(8) For the lower 8 bits, the TS0n bit is manipulated to start channel operation and the TT0n bit is manipulated to stop
channel operation. The channel status can be checked using the TE0n bit.
(9) During 16-bit operation, manipulating the TSH0n/TTH0n bits is invalid. The TS0n and TT0n bits are manipulated
to operate channel n. The TEH0n bit is not changed.
(10) For the 8-bit timer function, the simultaneous operation functions (one-shot pulse, PWM, and multiple PWM (16-pin
only)) cannot be used.
Remark n: Channel number (n = 1, 3)
Caution When channels 1 and 3 are used in 8-bit timer mode (SPLIT = 1), it is prohibited to read the TCR01H
and TDR01H registers or the TCR03H and TDR03H registers.
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