RL78/G10 CHAPTER 8 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER
R01UH0384EJ0311 Rev. 3.11 234
Dec 22, 2016
8.4 Operations of Clock Output/Buzzer Output Controller
One pin can be used to output a clock or buzzer sound.
The PCLBUZ0 pin outputs a clock/buzzer selected by the clock output select register 0 (CKS0).
8.4.1 Operation as output pin
The PCLBUZ0 pin is output as the following procedure.
<1> Set the bits in the port mode register (PM0/PM4), port register (P0/P4), and port mode control register 0 (PMC0)
that correspond to the pin on which the PCLBUZ0 function is multiplexed to 0.
<2> Select the output frequency with bits 0 to 2 (CCS00 to CCS02) of the clock output select register (CKS0) of the
PCLBUZ0 pin (output in disabled).
<3> Set bit 7 (PCLOE0) of the CKS0 register to 1 to enable clock/buzzer output.
Remark The controller used for outputting the clock starts or stops outputting the clock one clock after enabling or
disabling clock output (PCLOE0 bit) is switched. At this time, pulses with a narrow width are not output.
Figure 8-3 shows enabling or stopping output using the PCLOE0 bit and the timing of outputting the clock.
Figure 8-3. Timing of Clock Output from PCLBUZ0
PCLOE0
1 clock elapsed
Narrow pulses are not output
Clock output
Caution Entry to STOP mode within 1.5 clock cycles of the PCLBUZ0 pin output being disabled (PCLOE0 =
0) will shorten the width of the PCLBUZ0 pin output pulse. In such cases, only execute the STOP
instruction when at least 1.5 cycles of the clock used for PCLBUZ0 output have elapsed after the
PCLBUZ0 pin output has been disabled.
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