RL78/G10 CHAPTER 6 TIMER ARRAY UNIT
R01UH0384EJ0311 Rev. 3.11 206
Dec 22, 2016
6.9.3 Operation as PWM output function
Two channels can be used as a set to generate a pulse of any period and duty factor.
When channel 1 or 3 is used as an 8-bit timer (SPLIT0n = 1), only the lower 8-bit timer can be used as the slave
channel for the PWM output function.
The period and duty factor of the output pulse can be calculated by the following expressions.
Pulse period = {Set value of TDR0n (master) + 1} × Count clock period
Duty factor [%] = {Set value of TDR0p (slave)}/{Set value of TDR0n (master) + 1} × 100
0% output: Set value of TDR0p (slave) = 0000H (00H in 8-bit timer mode)
100% output: Set value of TDR0p (slave) ≥ {Set value of TDR0n (master) + 1}
Remark The duty factor exceeds 100% if the set value of TDR0p (slave) > (set value of TDR0n (master) + 1), the
actually output PWM waveform has a 100% duty factor.
The master channel operates in the interval timer mode. If the channel start trigger bit (TS0n) of timer channel start
register 0 (TS0) is set to 1, the interrupt request signal (INTTM0n) is output, the value set to timer data register 0n
(TDR0n) is loaded to timer count register 0n (TCR0n), and the counter counts down in synchronization with the count
clock (f
TCLK). When TCR0n reaches 0000H, INTTM0n is output, the value of the TDR0n register is loaded again to the
TCR0n register, and the counter counts down. This operation is repeated until the channel stop trigger bit (TT0n) of timer
channel stop register 0 (TT0) is set to 1.
During the PWM output function operation, the period until the master channel counts down to 0000H is the PWM
output (TO0p) cycle.
The slave channel operates in one-count mode. By using INTTM0n from the master channel as a start trigger, the
TCR0p register loads the value of the TDR0p register and TCR0p counts down to 0000H. When TCR0p reaches 0000H,
it outputs INTTM0p, and stops counting with TCR0p = FFFFH until the next start trigger (INTTM0n from the master
channel) is generated.
During the PWM output function operation, the period until the slave channel counts down to 0000H is the PWM output
(TO0p) duty.
PWM output (TO0p) goes to the active level one count clock (f
TCLK) after the master channel generates INTTM0n and
goes to the inactive level when the TCR0p register of the slave channel becomes 0000H.
Cautions 1. To rewrite both timer data register 0n (TDR0nH, TDR0nL) of the master channel and the TDR0pH
and TDR0pL registers of the slave channel, a write access is necessary at least four times. The
timing at which the values of the TDR0nH, TDR0nL, TDR0pH, and TDR0pL registers are loaded to
the TCR0nH, TCR0nL, TCR0pH, and TCR0pL registers is upon generation of INTTM0n of the
master channel. Thus, when rewriting is performed split before and after generation of INTTM0n
of the master channel, the TO0p pin cannot output the expected waveform. To rewrite all of the
TDR0nH, TDR0nL, TDR0pH, and TDR0pL registers, therefore, be sure to consecutively rewrite the
four registers immediately after INTTM0n is generated from the master channel.
2. To use the PWM output function in 8-bit timer mode, set 00H in TDR0nH of the master channel
and set the pulse period for the 8-bit timer. The TDR0nL register value should be set within the
range from 00H to FEH (0% to 100% output).
Remark n: Master channel number (n = 0, 2)
p: Slave channel number (n < p ≤ 3)
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