Renesas RL78/G10 User Manual

RL78/G10 CHAPTER 12 SERIAL ARRAY UNIT
R01UH0384EJ0311 Rev. 3.11 387
Dec 22, 2016
12.6.4 Procedure for processing errors that occurred during UART (UART0) communication
The procedure for processing errors that occurred during UART (UART0) communication is described in Figures 12-84
and 12-85.
Figure 12-84. Processing Procedure in Case of Parity Error or Overrun Error
Software Manipulation Hardware Status Remark
Reads serial data register 0n
(SDR0nL).
The BFF0n bit of the SSR0n register is
set to 0 and channel n is enabled to
receive data.
This is to prevent an overrun error if the
next reception is completed during error
processing.
Reads serial status register 0n (SSR0n). Error type is identified and the read
value is used to clear error flag.
Writes 1 to serial flag clear trigger
register 0n (SIR0n).
Error flag is cleared. Error can be cleared only during
reading, by writing the value read from
the SSR0n register to the SIR0n register
without modification.
Figure 12-85. Processing Procedure in Case of Framing Error
Software Manipulation Hardware Status Remark
Reads serial data register 0n
(SDR0nL).
The BFF0n bit of the SSR0n register is
set to 0 and channel n is enabled to
receive data.
This is to prevent an overrun error if the
next reception is completed during error
processing.
Reads serial status register 0n (SSR0n). Error type is identified and the read
value is used to clear error flag.
Writes serial flag clear trigger register 0n
(SIR0n).
Error flag is cleared. Error can be cleared only during
reading, by writing the value read from
the SSR0n register to the SIR0n register
without modification.
Sets the ST0n bit of serial channel stop
register 0 (ST0) to 1.
The SE0n bit of serial channel enable
status register 0 (SE0) is set to 0 and
channel n stops operating.
Synchronization with other party of
communication
Synchronization with the other party of
communication is re-established and
communication is resumed because it is
considered that a framing error has
occurred because the start bit has been
shifted.
Sets the SS0n bit of serial channel start
register 0 (SS0) to 1.
The SE0n bit of serial channel enable
status register 0 (SE0) is set to 1 and
channel n is enabled to operate.
Remark n = 0, 1

Renesas RL78/G10 Specifications

General

Brand	Renesas
Model	RL78/G10
Category	Motherboard
Language	English