RL78/G10 CHAPTER 12 SERIAL ARRAY UNIT
R01UH0384EJ0311 Rev. 3.11 281
Dec 22, 2016
12.2.1 Shift register
This is a 9-bit register that converts parallel data into serial data or vice versa.
During reception, it converts data input to the serial pin into parallel data.
When data is transmitted, the value set to this register is output as serial data from the serial output pin.
The shift register cannot be directly manipulated by program.
To read or write to the shift register, use the lower 8 bits of serial data register 0nL (SDR0nL).
8 7 6 5 4 3 2 1 0
Shift register
12.2.2 Serial data register 0nL (SDR0nL)
The SDR0nL register is used as a transmit/receive buffer register of channel n.
When data is received, parallel data converted by the shift register is stored in the SDR0nL register. When data is
to be transmitted, set transmit data to be transferred to the shift register in the SDR0nL register.
The length of data stored in the SDR0nL register is as follows, depending on the setting of bit 0 (DLS0n0) of serial
communication operation setting register 0n (SCR0nL), regardless of the output sequence of the data.
• 7-bit data length (stored in bits 0 to 6 of SDR0nL register)
• 8-bit data length (stored in bits 0 to 7 of SDR0nL register)
The SDR0nL register is set by an 8-bit memory manipulation instruction when the operation is enabled (SE0n = 1).
Writing to the SDR0nL register is prohibited when the operation is stopped (SE0n = 0).
Reset signal generation clears the SDR0nL register to 00H.
Eight-bit memory manipulation instructions are used to set the SDR0nL register as a buffer for an SFR listed below,
in accord with the communications protocol in use.
• During CSIp communication: SIOp (CSIp data register)
• During UART0 reception: RXD0 (UART0 receive data register)
• During UART0 transmission: TXD0 (UART0 transmit data register)
• During IIC00 communication: SIO00 (IIC00 data register)
Remark n: Channel number (n = 0, 1), p: CSI number (p = 00, 01)
Figure 12-2. Format of Serial Data Register 0nL (SDR0nL) (n = 0, 1)
Address: FFF10H (SDR00L), FFF12H (SDR01L) After reset: 00H R/W
Symbol
7 6 5 4 3 2 1 0
SDR0nL
Remark For the function of the SDR0nH register, see 12.3 Registers Controlling Serial Array Unit.
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