RL78/G10 CHAPTER 6 TIMER ARRAY UNIT
R01UH0384EJ0311 Rev. 3.11 154
Dec 22, 2016
6.6.5 Timer interrupt and TO0n pin output at count operation start
In the interval timer mode or capture mode, the MD0n0 bit in timer mode register 0n (TMR0n) sets whether or not to
generate a timer interrupt at count start.
When MD0n0 is set to 1, the count operation start timing can be known by the interrupt request signal (INTTM0n)
generation.
In the other modes, neither INTTM0n at count operation start nor TO0n output is controlled.
Figure 6-37 shows operation examples when the interval timer mode (TOE0n = 1, TOM0n = 0) is set.
Figure 6-37. Operation Examples of Timer Interrupt at Count Operation Start and TO0n Output
(a) When MD0n0 is set to 1
TCR0n
TE0n
TO0n
INTTM0n
Count operation start
(b) When MD0n0 is set to 0
TCR0n
TE0n
TO0n
INTTM0n
Count operation start
When MD0n0 is set to 1, the interrupt request signal (INTTM0n) is output at count operation start, and TO0n performs a
toggle operation.
When MD0n0 is set to 0, the interrupt request signal (INTTM0n) is not output at count operation start, and TO0n does
not change either. After counting one cycle, INTTM0n is output and TO0n performs a toggle operation.
Remark n: Channel number
n = 0, 1 (for 10-pin products); n = 0 to 3 (for 16-pin products)
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