RL78/G10 CHAPTER 6 TIMER ARRAY UNIT
R01UH0384EJ0311 Rev. 3.11 188
Dec 22, 2016
6.9 Simultaneous Channel Operation Function of Timer Array Unit
6.9.1 Operation as one-shot pulse output
By using two channels as a set, a one-shot pulse having any delay (output delay time) can be generated from the
signal input to the TI0n pin.
In addition, by setting TS0n to 1 by software, the count down can be started during the period of TE0n = 1.
The delay time and one-shot pulse width can be calculated by the following expressions.
Delay time = {Set value of TDR0n (master) + 2} × Count clock period
One-shot pulse width = {Set value of TDR0p (slave)} × Count clock period
Caution The TI0n pin input is sampled using the operating clock (f
MCK) selected with the CKS0n1 bit of
timer mode register 0n (TMR0n), so an error of one cycle of the operating clock (f
MCK) occurs.
The master channel operates in the one-count mode and counts the delays. Timer count register 0n (TCR0n) of the
master channel starts operating upon start trigger detection and loads the value of timer data register 0n (TDR0n).
The TCR0n register counts down from the value of the TDR0n register it has loaded, in synchronization with the count
clock (f
TCLK). When TCR0n = 0000H, it outputs INTTM0n and stops counting until the next start trigger is detected.
The slave channel operates in the one-count mode and counts the one-shot pulse width. The TCR0p register of the
slave channel starts operation using INTTM0n of the master channel as a start trigger, and loads the value of the TDR0p
register. The TCR0p register counts down from the value of The TDR0p register it has loaded, in synchronization with the
count value (f
TCLK). When TCR0p = 0000H, it outputs INTTM0p and stops counting with TCR0p = FFFFH until the next
start trigger (INTTM0n of the master channel) is detected. The output level of TO0p becomes active one count clock
(f
TCLK) after generation of INTTM0n from the master channel, and inactive when TCR0p = 0000H.
Caution The timing of loading of timer data register 0n (TDR0n) of the master channel is different from that of
the TDR0p register of the slave channel. If the TDR0n and TDR0p registers are rewritten during
operation, therefore, an illegal waveform may be output. Rewrite the TDR0n register after INTTM0n is
generated and the TDR0p register after INTTM0p is generated.
Remark n: Master channel number (n = 0, 2)
p: Slave channel number (n < p ≤ 3)
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