RL78/G10 CHAPTER 11 COMPARATOR
R01UH0384EJ0311 Rev. 3.11 271
Dec 22, 2016
11.4 Comparator Operation
The C0MON bit in the COMPMDR register is set to 1 when the analog input voltage on the IVCMP0 pin is higher than
the reference voltage. When lower, the C0MON bit is set to 0.
When using the comparator 0 interrupt (INTCMP0), set the C0IE bit in the COMPOCR register to 1 (interrupt request
enabled). If the comparison result changes at this time, a comparator 0 interrupt request signal is generated. For details on
the comparator 0 interrupt request, refer to 11.4.2 Comparator 0 Interrupt Operation.
Figure 11-6 shows an example of the comparator 0 operation (no digital filter (C0FCK1 and C0FCK0 in COMPFIR =
00B), both-edge detection on an interrupt (C0EDG = 1).
Figure 11-6. Example of Comparator 0 Operation (No Digital Filter, Both-Edge Detection on Interrupt)
Reference voltage
(IVREF0 or internal
reference voltage
(0.815 V (typ.))
Analog input voltage (V)
C0MON bit in
COMPMDR register
Note
Comparator 0 interrupt
(INTCMP0)
1
0
1
0
(A) (B) (A) (B
)
Note The output delay time depends on the comparator operating mode. For details, see 24.6.2
Comparator characteristics.
Caution When the rising edge is specified as an effective edge for an interrupt (C0EDG = 0 and C0EPO = 0),
INTCMP0 only changes at (A).
When the falling edge is specified as an effective edge for an interrupt (C0EDG = 0 and C0EPO = 1),
INTCMP0 only changes at (B).
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