RL78/G10 CHAPTER 10 A/D CONVERTER
R01UH0384EJ0311 Rev. 3.11 253
Dec 22, 2016
10.4 A/D Converter Conversion Operations
The A/D converter conversion operations are described below.
<1> The voltage input to the selected analog input channel is sampled by the sample & hold circuit.
<2> When sampling has been done for a certain time, the sample & hold circuit is placed in the hold state and the
sampled voltage is held until the A/D conversion operation has ended.
<3> Bit 9 of the successive approximation register (SAR) is set. The series resistor string voltage tap is set to (1/2)
V
DD by the tap selector.
<4> The voltage difference between the series resistor string voltage tap and sampled voltage is compared by the
voltage comparator. If the analog input is greater than (1/2) V
DD, the MSB bit of the SAR register remains set to 1.
If the analog input is smaller than (1/2) VDD, the MSB bit is reset to 0.
<5> Next, bit 8 of the SAR register is automatically set to 1, and the operation proceeds to the next comparison. The
series resistor string voltage tap is selected according to the preset value of bit 9, as described below.
• Bit 9 = 1: (3/4) V
DD
• Bit 9 = 0: (1/4) V
DD
The voltage tap and sampled voltage are compared and bit 8 of the SAR register is manipulated as follows.
• Sampled voltage ≥ Voltage tap: Bit 8 = 1
• Sampled voltage < Voltage tap: Bit 8 = 0
<6> Comparison is continued in this way up to bit 0 of the SAR register.
<7> Upon completion of the comparison of 10 bits, an effective digital result value remains in the SAR register, and
the result value is transferred to the A/D conversion result register (ADCRH, ADCRL) and then latched.
At the same time, the A/D conversion end interrupt request (INTAD) is generated.
After A/D conversion ends, the ADCS bit is automatically cleared to 0, and the system enters the A/D conversion
standby status.
Remark Two types of the A/D conversion result registers are available.
• ADCRH register (8 bits): Store eight higher-order bits of the result of 10-bit resolution A/D conversion or the
result of 8-bit resolution A/D conversion.
• ADCRL register (2 bits): Store two lower-order bits of the result of 10-bit resolution A/D conversion.
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