RL78/G10 CHAPTER 6 TIMER ARRAY UNIT
R01UH0384EJ0311 Rev. 3.11 178
Dec 22, 2016
6.8.5 Operation as input signal high-/low-level width measurement
By starting counting at one edge of the TI0n pin input and capturing the number of counts at another edge, the signal
width (high-level width/low-level width) of TI0n can be measured. The signal width of TI0n can be calculated by the
following expression.
Signal width of TI0n input = Period of count clock × ((10000H × TSR0n: OVF) + (Capture value of TDR0n + 1))
Caution The TI0n pin input is sampled using the operating clock (f
MCK) selected with the CKS0n1 bit of
timer mode register 0n (TMR0n), so an error of one cycle of the operating clock (fMCK) occurs.
Timer count register 0n (TCR0n) operates as an up counter in the capture & one-count mode.
When the channel start trigger bit (TS0n) of timer channel start register 0 (TS0) is set to 1, the TE0n bit is set to 1 and
the TI0n pin start edge detection wait status is set.
When the TI0n pin input start edge (rising edge of the TI0n pin input when the high-level width is to be measured) is
detected, the counter counts up from 0000H in synchronization with the count clock. When the valid capture edge (falling
edge of the TI0n pin input when the high-level width is to be measured) is detected later, the count value is transferred to
timer data register 0n (TDR0n) and, at the same time, INTTM0n is output. If the counter overflows at this time, the OVF bit
of timer status register 0n (TSR0n) is set to 1. If the counter does not overflow, the OVF bit is cleared. The TCR0n
register stops at the value “value transferred to the TDR0n register + 1”, and the TI0n pin start edge detection wait status
is set. After that, the above operation is repeated.
As soon as the count value has been captured to the TDR0n register, the OVF bit of the TSR0n register is updated
depending on whether the counter overflows during the measurement period. Therefore, the overflow status of the
captured value can be checked.
If the counter reaches a full count for two or more periods, it is judged to be an overflow occurrence, and the OVF bit of
the TSR0n register is set to 1. However, a normal interval value cannot be measured for the OVF bit, if two or more
overflows occur.
Whether the high-level width or low-level width of the TI0n pin is to be measured can be selected by using the CIS0n1
and CIS0n0 bits of the TMR0n register.
Because this function is used to measure the signal width of the TI0n pin input, the TS0n bit cannot be set to 1 while
the TE0n bit is 1.
CIS0n1, CIS0n0 of TMR0n register = 10B: Low-level width is measured.
CIS0n1, CIS0n0 of TMR0n register = 11B: High-level width is measured.
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