RL78/G10 CHAPTER 6 TIMER ARRAY UNIT
R01UH0384EJ0311 Rev. 3.11 173
Dec 22, 2016
6.8.4 Operation as input pulse interval measurement
The count value can be captured on detection of a valid edge of TI0n pin input and the interval of the pulse input to
TI0n pin can be measured. In addition, the count value can be captured by setting TS0n to 1 by software during the period
of TE0n = 1.
For the UART0 baud rate correction, set bit 1 (ISC1) of the input switch control register (ISC) to 1.
In the following descriptions, read TI0n as RxD0. When the ISC1 bit is set to 1, the input signal of the serial data input
(RxD0) pin is selected as a timer input (TI01). The width at the baud rate (transfer rate) of the other party in
communications can be measured by using the input pulse interval measurement mode with the input edge signal of the
start bit as a trigger.
The input pulse interval can be calculated by the following expression.
TI0n input pulse interval = Period of count clock × ((10000H × TSR0n: OVF) + (Capture value of TDR0n + 1))
Caution The TI0n pin input is sampled using the operating clock (f
MCK) selected with the CKS0n1 bit of
timer mode register 0n (TMR0n), so an error of one cycle of the operating clock (f
MCK) occurs.
Timer count register 0n (TCR0n) operates as an up counter in the capture mode.
When the channel start trigger bit (TS0n) of timer channel start register 0 (TS0) is set to 1, the TCR0n register counts
up from 0000H in synchronization with the count clock.
When the TI0n pin input valid edge is detected, the count value of the TCR0n register is transferred (captured) to timer
data register 0n (TDR0n) and, at the same time, the TCR0n register is cleared to 0000H, and the INTTM0n is output. If
the counter overflows at this time, the OVF bit of timer status register 0n (TSR0n) is set to 1. If the counter does not
overflow, the OVF bit is cleared. After that, the above operation is repeated.
As soon as the count value has been captured to the TDR0n register, the OVF bit of the TSR0n register is updated
depending on whether the counter overflows during the measurement period. Therefore, the overflow status of the
captured value can be checked.
If the counter reaches a full count for two or more periods, it is judged to be an overflow occurrence, and the OVF bit of
the TSR0n register is set to 1. However, a normal interval value cannot be measured for the OVF bit, if two or more
overflows occur.
Set the STS0n2 to STS0n0 bits of the TMR0n register to 001B to use the valid edges of TI0n as a start trigger and a
capture trigger.
In addition, a software operation (TS0n = 1) can be used as a capture trigger, instead of using the TI0n pin input. When
TS0n is set to 1 during TE0n = 1, the count value is captured in synchronization with the operating clock (f
MCK).
Figure 6-52. Block Diagram of Operation as Input Pulse Interval Measurement
Interrupt signal
(INTTM0n)
Interrupt
controller
Clock selection
Trigger selection
Operation clock
CK00
CK01
Edge
detection
TI0n pin
TS0n
Timer counter
register 0n (TCR0n)
Timer data
register 0n (TDR0n)
Noise
filter
TNFEN0n
Remark n: Channel number
n = 0, 1 (for 10-pin products); n = 0 to 3 (for 16-pin products)
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