RL78/G10 CHAPTER 13 SERIAL INTERFACE IICA
R01UH0384EJ0311 Rev. 3.11 411
Dec 22, 2016
13.2 Configuration of Serial Interface IICA
Serial interface IICA includes the following hardware.
Table 13-1. Configuration of Serial Interface IICA
Item Configuration
Registers IICA shift register 0 (IICA0)
Slave address register 0 (SVA0)
Control registers Peripheral enable register 0 (PER0)
IICA control register 00 (IICCTL00)
IICA status register 0 (IICS0)
IICA flag register 0 (IICF0)
IICA control register 01 (IICCTL01)
IICA low-level width setting register 0 (IICWL0)
IICA high-level width setting register 0 (IICWH0)
Port mode register 0 (PM0)
Port register 0 (P0)
Port output mode register 0 (POM0)
Port mode control register 0 (PMC0)
(1) IICA shift register 0 (IICA0)
The IICA0 register is used to convert 8-bit serial data to 8-bit parallel data and vice versa in synchronization with
the serial clock. The IICA0 register can be used for both transmission and reception.
The actual transmit and receive operations can be controlled by writing and reading operations to the IICA0 register.
Cancel the wait state and start data transfer by writing data to the IICA0 register during the wait period.
The IICA0 register can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears IICA0 to 00H.
Figure 13-3. Format of IICA Shift Register 0 (IICA0)
Symbol
IICA0
Address: FFF50H After reset: 00H R/W
76543210
Cautions 1. Do not write data to the IICA0 register during data transfer.
2. Write or read the IICA0 register only during the wait period. Accessing the IICA0
register in a communication state other than during the wait period is prohibited.
When the device serves as the master, however, the IICA0 register can be written
only once after the communication trigger bit (STT0) is set to 1.
3. When communication is reserved, write data to the IICA0 register after the interrupt
triggered by a stop condition is detected.
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