RL78/G10 CHAPTER 6 TIMER ARRAY UNIT
R01UH0384EJ0311 Rev. 3.11 142
Dec 22, 2016
6.5.3 Counter operation
Here, the counter operation in each mode is explained.
(1) Interval timer mode operation
<1> Operation is enabled (TE0n = 1) by writing 1 to the TS0n bit. Timer count register 0n (TCR0n) holds the
initial value until count clock (fTCLK) generation.
<2> A start trigger is generated at the first count clock after operation is enabled.
<3> When the MD0n0 bit is set to 1, INTTM0n is generated by the start trigger.
<4> By the first count clock after the operation enable, the value of timer data register 0n (TDR0n) is loaded to
the TCR0n register and counting starts in the interval timer mode.
<5> When the TCR0n register counts down and its count value is 0000H, INTTM0n is generated in the next
count clock and the value of timer data register 0n (TDR0n) is loaded to the TCR0n register and counting
keeps on.
Figure 6-24. Operation Timing (In Interval Timer Mode)
Caution In the first cycle operation of count clock (f
TCLK) after writing the TS0n bit, an error of a maximum
of one cycle of the count clock (f
TCLK) is generated since count start delays until count clock
(f
TCLK) has been generated. When the information on count start timing is necessary, the interrupt
request signal (INTTM0n) can be generated at count start by setting MD0n0 = 1.
Remark f
MCK, the start trigger detection signal, and INTTM0n become active for one clock period in
synchronization with fCLK.
fMC
(fTCLK)
m
TS0n (Write)
TE0n
Start trigge
detection signal
TCR0n
Initial
value
m
TDR0n
INTTM0n
When MD0n0 is set to 1
<1>
<3>
<4>
m−1
0000
m
0001
<2>
<5>
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