RL78/G10 CHAPTER 6 TIMER ARRAY UNIT
R01UH0384EJ0311 Rev. 3.11 170
Dec 22, 2016
Figure 6-50. Example of Set Contents of Registers During Operation as Frequency Divider (1/2)
(a) Timer mode register 0n (TMR0nH, TMR0nL)
TMR0nH TMR0nL
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
TMR0n
CKS0n1
1/0
0
0
CCS0n
1
S
Note
0
STS0n2
0
STS0n1
0
STS0n0
0
CIS0n1
1/0
CIS0n0
1/0
0
0
MD0n3
0
MD0n2
0
MD0n1
0
MD0n0
1/0
Operation mode of channel 0
000B: Interval timer
Setting of operation when counting is started
0: Neither generates INTTM0n nor inverts
timer output when counting is started.
1: Generates INTTM0n and inverts timer
output when counting is started.
Selection of TI00 pin input edge
00B: Detects falling edge.
01B: Detects rising edge.
10B: Detects both edges.
11B: Setting prohibited
Start trigger selection
000B: Selects only software start.
Setting of SPLIT0n bit (Channel 3)
0: 16-bit timer
Count clock selection
1: Selects the TI00 pin input valid edge.
Operation clock (f
MCK) selection
0: Selects CK00 as operation clock of channel 0.
1: Selects CK01 as operation clock of channel 0.
(b) Timer output register 0 (TO0)
Bit n
TO0
TO0n
1/0
0: Outputs 0 from TO0n.
1: Outputs 1 from TO0n.
(c) Timer output enable register 0 (TOE0)
Bit n
TOE0
TOE0n
1/0
0: Stops the TO0n output operation by counting operation (the level set in the TO0n bit is output from the
TO0n pin.).
1: Enables the TO0n output operation by counting operation (output from the TO0n pin is toggled).
Note TMR03: SPLIT03 bit
TMR00: 0 fixed
Remark n: Channel number
n = 0 (for 10-pin products); n = 0, 3 (for 16-pin products)
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