RL78/G10 CHAPTER 6 TIMER ARRAY UNIT
R01UH0384EJ0311 Rev. 3.11 204
Dec 22, 2016
Figure 6-73. Procedure for Two-channel Input with One-shot Pulse Output Function (1/2)
Software Operation Hardware Status
TAU
default
setting
Power-off status
(Clock supply is stopped and writing to SFR of the TAU
is disabled.)
Sets the TAU0EN bit of peripheral enable registers 0
(PER0) to 1 (when the TAU0EN bit is 0, read/write
operation is disabled).
Power-on status. Each channel stops operating.
(Clock supply is started and writing to SFR of the TAU is
enabled.)
Sets timer clock select register 0 (TPS0).
Determines operating clock (CK00 and CK01) for each
channel.
Channel
default
setting
Sets noise filter enable register 1 (NFEN1).
Sets timer mode register 0n, 0p (TMR0n, TMR0p)
(determines operation mode for each channel and
selects the detection edge).
Channel stops operating.
Sets master channel
Sets delay (output delay time) to timer data register 0n
(TDR0n) (for the access procedure to the TDR0nH
and TDR0nL registers, see 6.2.2 Timer data register
0n (TDR0n)).
Clears the target bit of timer output mode register 0
(TOM0) to 0 (master channel output mode).
Clears the target bit of the TOL0 register to 0.
Clears the target bit of the timer output enable register
0 (TOE0) to 0.
Sets slave channel.
Sets the target bit of timer output mode register 0
(TOM0) to 1 (slave channel output mode).
Sets the target bit of the TOL0 register.
Sets the TO0p bit and determines default level of the
TO0p output.
Sets the TOE0p bit to 1 and enables operation of TO0p.
Clears the port register and port mode register to 0.
(output mode is set)
The TO0p pin goes into Hi-Z state.
(The port mode register is set to input mode.)
TO0p does not change because channel stops operating.
(The TO0p pin is not affected even if the TO0p bit is
modified).
The level set in the TO0p bit is output from the TO0p pin.
Remark n: Master channel number (n = 0, 2)
p: Slave channel number (p = 3)
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