RL78/G10 CHAPTER 6 TIMER ARRAY UNIT
R01UH0384EJ0311 Rev. 3.11 208
Dec 22, 2016
Figure 6-75. Example of Basic Timing of Operation as PWM Output Function
TS0n
TE0n
TDR0n
TCR0n
TO0n
INTTM0n
a b
0000H
TS0p
TE0p
TDR0p
TCR0p
TO0p
INTTM0p
c
c
d
0000H
c
d
Master
channel
Slave
channel
a+1
a+1
b+1
FFFFH
FFFFH
Remark 1. n: Master channel number (n = 0, 2)
p: Slave channel number (n < p ≤ 3)
2. TS0n, TS0p: Bit n, p of timer channel start register 0 (TS0)
TE0n, TE0p: Bit n, p of timer channel enable status register 0 (TE0)
TCR0n, TCR0p: Timer count registers 0n, 0p (TCR0n, TCR0p)
TDR0n, TDR0p: Timer data registers 0n, 0p (TDR0n, TDR0p)
TO0n, TO0p: TO0n and TO0p pins output signal