Renesas RL78/G10 User Manual

RL78/G10 CHAPTER 13 SERIAL INTERFACE IICA
R01UH0384EJ0311 Rev. 3.11 445
Dec 22, 2016
Figure 13-24 shows the communication reservation timing.
Figure 13-24. Communication Reservation Timing
21 3456 21 3456789
SCLA0
SDAA0
Program processing
Hardware processing
Write to
IICA0
Set SPD0
and
INTIICA0
STT0 = 1
Communi-
cation
reservation
Set
STD0
Generate by master device with bus mastership
Remark IICA0: IICA shift register 0
STT0: Bit 1 of IICA control register 00 (IICCTL00)
STD0: Bit 1 of IICA status register 0 (IICS0)
SPD0: Bit 0 of IICA status register 0 (IICS0)
Communication reservations are accepted via the timing shown in Figure 13-25. After bit 1 (STD0) of the IICA
status register 0 (IICS0) is set to 1, a communication reservation can be made by setting bit 1 (STT0) of IICA
control register 00 (IICCTL00) to 1 before a stop condition is detected.
Figure 13-25. Timing for Accepting Communication Reservations
SCLA0
SDAA0
STD0
SPD0
Standby mode (Communication can be reserved by setting STT0 to 1 during this period.)
Figure 13-26 shows the communication reservation protocol.

Renesas RL78/G10 Specifications

General

Brand	Renesas
Model	RL78/G10
Category	Motherboard
Language	English