RL78/G10 CHAPTER 14 INTERRUPT FUNCTIONS
R01UH0384EJ0311 Rev. 3.11 496
Dec 22, 2016
Table 14-1. Interrupt Source List (10-pin Products)
Interrupt Type
Default Priority
Note 1
Interrupt Source
Internal
/External
Vector Table
Address
Basic
Configuration
Type
Note 2
Name Trigger
Maskable
0 INTWDTI
Watchdog timer interval
(75% of overflow time +3/(4 × fIL))
Internal 0004H (a)
1 INTP0 Pin input edge detection External 0006H (b)
2 INTP1 0008H
3 INTST0/
UART0 transmission transfer end or buffer empty
interrupt/CSI00 transfer end or buffer empty
interrupt/IIC00 transfer end
Internal 000AH (a)
INTCSI00/
INTIIC00
4 INTSR0 UART0 reception transfer end 000CH
5 INTSRE0 UART0 reception communication error occurrence 000EH
6 INTTM01H
End of counting or start of operations by timer channel
1 (at higher 8-bit timer operation)
0010H
7 INTTM00
End of counting, completion of capture, or start of
operations by timer channel 0
0012H
8 INTTM01
End of counting, completion of capture, or start of
operations by timer channel 1 (at 16-bit or lower 8-bit
timer operation)
0014H
9 INTAD End of A/D conversion 0016H
10 INTKR Key return signal detection External 0018H (c)
Software
−
BRK Execution of BRK instruction
−
007EH (d)
Reset
−
RESET RESET pin input
−
0000H
−
SPOR Selectable power-on-reset
WDT Overflow of watchdog timer
TRAP Execution of illegal instruction
Note 3
Notes 1. The default priority determines the sequence of interrupts if two or more maskable interrupts occur
simultaneously. Zero indicates the highest priority and 10 indicates the lowest priority.
2. Basic configuration types (a) to (d) correspond to (a) to (d) in Figure 14-1.
3. When the instruction code in FFH is executed.
No reset is issued even if an illegal instruction is executed during emulation with the on-chip debug emulator.
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