RL78/G10 CHAPTER 6 TIMER ARRAY UNIT
R01UH0384EJ0311 Rev. 3.11 162
Dec 22, 2016
Figure 6-43. Procedure for Operating Interval Timer/Outputting Square Wave (2/2)
Software Operation Hardware Status
TAU
stop
To hold the TO0n pin output level
Clears the TO0n bit to 0 after the value to
be held (output latch) is set in the port register.
The TO0n pin output level is held by port function.
Clears the TAU0EN bit of the PER0 register to 0. Power-off status
(Clock supply is stopped and SFR of the TAU is initialized.)
Remark n: Channel number
n = 0, 1 (for 10-pin products); n = 0 to 3 (for 16-pin products)
Caution When channels 1 and 3 are used in 8-bit timer mode (SPLIT = 1), it is prohibited to read the TCR01H and
TDR01H registers or the TCR03H and TDR03H registers.
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