RL78/G10 CHAPTER 3 CPU ARCHITECTURE
R01UH0384EJ0311 Rev. 3.11 52
Dec 22, 2016
Figure 3-30. Example of ES:word[BC]
X0000H
rp(BC)
X0000H
ES
ES: word [BC]
OP-code
Low Addr.
High Addr.
Specifies a
64-Kbyte area
Offset
<3>
<3>
<1>
Instruction code
<1> <2>
<2>
<3>
<1>
<2>
Target memory
Memory
XFFFFH
Array of
word-sized
data
Address of a word within an array
The ES register <1> specifies a 64-Kbyte area within the
overall 1-Mbyte space as the four higher-order bits, X, of
the address range.
“word” <2> specifies the address where the target array of
word-sized data starts in the 64-Kbyte area specified in the
ES register <1>.
A pair of registers <3> specifies an offset within the array
to the target location in memory.
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