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4.6
CIRCUIT BRE
AKER FAIL PRO
TECTION
I< Pick-up
1.1 X setting +/- 5% or 20 mA
, whichever is greater
I< Drop-off
Setting +/- 5% or 20 mA
, whichever is greater
Timers
+/- 2% or 50 ms, whichever is greater
Reset time
< 15 ms (fully offset current w
aveform considered)
P64x
Chapter 21 - Technical Specifications
P64x-TM-EN-1.3
463
486
488
Table of Contents
Default Chapter
3
Table of Contents
3
Chapter 1 Introduction
25
Rear Serial Port
26
Figure 137: TCS Scheme
26
Chapter Overview
27
Cip
27
Foreword
28
Target Audience
28
Typographical Conventions
28
Cip
28
Nomenclature
29
Cip
29
Product Scope
30
Product Versions
30
Cip
30
Ordering Options
31
Figure 1: P64X Version Evolution
31
Features and Functions
32
Protection Functions
32
Control Functions
32
Measurement Functions
33
Communication Functions
33
Compliance
34
Functional Overview
35
Figure 2: Functional Overview
35
Chapter 2 Safety Information
37
Chapter Overview
39
Health and Safety
40
Symbols
41
Installation, Commissioning and Servicing
42
Lifting Hazards
42
Electrical Hazards
42
UL/CSA/CUL Requirements
43
Fusing Requirements
43
Equipment Connections
44
Protection Class 1 Equipment Requirements
44
Pre-Energisation Checklist
45
Peripheral Circuitry
45
Upgrading/Servicing
46
Decommissioning and Disposal
47
Standards Compliance
48
EMC Compliance: 2004/108/EC
48
Product Safety: 2006/95/EC
48
R&TTE Compliance
48
UL/CUL Compliance
48
ATEX Compliance
48
Chapter 3 Hardware Design
51
Chapter Overview
53
Hardware Architecture
54
Figure 3: Hardware Architecture
54
Mechanical Implementation
55
Housing Variants
55
Figure 4: Exploded View of IED
55
List of Boards
56
Front Panel
58
Front Panel Compartments
58
Figure 5: Front Panel (60TE)
58
HMI Panel
59
Front Serial Port (SK1)
59
Figure 6: HMI Panel
59
Front Parallel Port (SK2)
60
Fixed Function Leds
60
Function Keys
60
Programable Leds
61
Rear Panel
62
Figure 7: Rear View of Populated Case
62
Figure 8: Terminal Block Types
63
Boards and Modules
64
Pcbs
64
Subassemblies
64
Figure 9: Rear Connection to Terminal Block
64
Main Processor Board
65
Figure 10: Main Processor Board
65
Power Supply Board
66
Figure 11: Power Supply Board
66
Figure 12: Power Supply Assembly
67
Watchdog
68
Figure 13: Power Supply Terminals
68
Rear Serial Port
69
Figure 14: Watchdog Contact Terminals
69
Input Module - 1 Transformer Board
70
Figure 15: Rear Serial Port Terminals
70
Figure 16: Input Module - 1 Transformer Board
70
Input Module Circuit Description
71
Figure 17: Input Module Schematic
71
Frequency Response
72
Figure 18: Frequency Response
72
Transformer Board
73
Figure 19: Transformer Board
73
Input Board
74
Figure 20: Input Board
74
Standard Output Relay Board
75
Figure 21: Standard Output Relay Board - 8 Contacts
75
IRIG-B Board
76
Figure 22: IRIG-B Board
76
Fibre Optic Board
77
Figure 23: Fibre Optic Board
77
Rear Communication Board
78
Ethernet Board
78
Figure 24: Rear Communication Board
78
Figure 25: Ethernet Board
78
Redundant Ethernet Board
80
Figure 26: Redundant Ethernet Board
80
RTD Board
82
Figure 27: RTD Board
82
CLIO Board
83
Figure 28: RTD Board
83
High Break Output Relay Board
85
Figure 29: High Break Relay Output Board
85
Figure 30: High Break Contact Operation
86
Chapter 4 Software Design
87
Chapter Overview
89
Sofware Design Overview
90
Figure 31: Software Architecture
90
System Level Software
91
Real Time Operating System
91
System Services Software
91
Self-Diagnostic Software
91
Startup Self-Testing
91
System Boot
91
System Level Software Initialisation
92
Platform Software Initialisation and Monitoring
92
Continuous Self-Testing
92
Platform Software
94
Record Logging
94
Settings Database
94
Interfaces
94
Protection and Control Functions
95
Acquisition of Samples
95
Frequency Tracking
95
Direct Use of Sample Values
95
Fourier Signal Processing
95
Programmable Scheme Logic
96
Figure 32: Frequency Response (Indicative Only)
96
Event Recording
97
Disturbance Recorder
97
Fault Locator
97
Function Key Interface
97
Chapter 5 Configuration
99
Chapter Overview
101
Using the HMI Panel
102
Navigating the HMI Panel
103
Getting Started
103
Figure 33: Navigating the HMI
103
Default Display
104
Default Display Navigation
105
Figure 34: Default Display Navigation
105
Password Entry
106
Processing Alarms and Records
106
Menu Structure
107
Changing the Settings
108
Direct Access (the Hotkey Menu)
109
Setting Group Selection Using Hotkeys
109
Control Inputs
109
Function Keys
110
Configuring the Data Protocols
112
Courier Configuration
112
DNP3 Configuration
113
DNP3 Configurator
114
MODBUS Configuration
116
IEC 61850 Configuration
117
IEC 61850 Configuration Banks
118
IEC 61850 Network Connectivity
118
Date and Time Configuration
119
Time Zone Compensation
119
Daylight Saving Time Compensation
119
Phase Rotation
120
CT and VT Reversal
120
Chapter 6 Transformer Differential Protection
121
Chapter Overview
123
Transformer Differential Protection Principles
124
Through Fault Stability
124
Bias Current Compensation
124
Three-Phase Transformer Connection Types
125
Figure 35: Compensation Using Biased Differential Characteristic
125
Figure 36: Transformer Winding Connections - Part 1
127
Phase and Amplitude Compensation
128
Figure 37: Transformer Winding Connections - Part 2
128
Zero Sequence Filtering
129
Magnetising Inrush Restraint
129
Figure 38: Magnetising Inrush Phenomenon
129
Overfluxing Restraint
130
Figure 39: Typical Overflux Current Waveform
130
Implementation
131
Defining the Power Transformer
131
Selecting the Current Inputs
131
Phase Correction
132
Ratio Correction
132
CT Parameter Mismatch
133
Figure 40: CT Parameter Mismatch Logic Diagram
133
Setting up Zero Sequence Filtering
134
Tripping Characteristics
134
High-Set Function
135
Circuitry Fail Alarm
135
Figure 41: Transformer Biased Tripping Characteristic
135
Tripping Characteristic Stability
136
Maximum Bias
136
Delayed Bias
136
Transient Bias
136
CT Saturation Technique
137
No Gap Detection Technique
137
External Fault Detection Technique
137
Figure 42: Transient Bias Characteristic
137
Current Transformer Supervision
138
Figure 43: Time to Saturation - External an Fault
138
Circuitry Fail Alarm
139
Figure 44: Effect of CTS Restrain
139
Figure 45: Bias Characteristic with Circuitry Fail Alarm
139
Differential Biased Trip Logic
140
Figure 46: Differential Biased Trip Logic
140
Harmonic Blocking
141
2Nd Harmonic Blocking
141
Figure 47: 2Nd Harmonic Blocking Process
141
2Nd Harmonic Blocking Logic
142
5Th Harmonic Blocking Implementation
142
Figure 48: 2Nd Harmonic Blocking Logic
142
5Th Harmonic Setting Guideline
143
Geomagnetic Disturbances
143
Overall Harmonic Blocking Logic
143
Figure 49: 5Th Harmonic Blocking Process
143
Figure 50: Differential Protection Blocking Mechanisms
144
Application Notes
145
Setting Guidelines
145
Example 1: Two-Winding Transformer - no Tap Changer
146
Figure 51: Triple Slope Characteristic
146
Figure 52: P642 Used to Protect a Two Winding Transformer
146
Example 2: Autotransformer with Loaded Delta Winding
148
Figure 53: P645 Used to Protect an Autotransformer with Loaded Delta Winding
149
Example 3: Autotransformer with Unloaded Delta Winding
151
Figure 54: P643 Used to Protect an Autotransformer with Unloaded Delta Winding
152
Figure 55: Unloaded Delta - Current Distribution
153
Setting Guidelines for Short-Interconnected Biased Differential Protection
154
Figure 56: Single Bus Differential Protection Zone
155
Setting Guidelines for Shunt Reactor Biased Differential Protection
157
Figure 57: Busbar Biased Differential Protection
157
Figure 58: Shunt Reactor Single Line Diagram
158
Setting Guidelines for Using Spare CT Inputs
159
Setting Guidelines for Reference Vector Group
160
Figure 59: P643 Using Spare CT Input for Overcurrent Protection
160
Stub Bus Application
161
Stub Bus Implementation
161
Figure 60: Stub Bus Arrangement
161
Stub Bus Scheme
162
Transformer Differential Protection CT Requirements
162
CT Requirements - Transformer Application
162
Figure 61: Stub Bus Scheme Logic
162
CT Requirements - Small Busbar Application
163
Chapter 7 Transformer Condition Monitoring
165
Chapter Overview
167
Thermal Overload Protection
168
Thermal Overload Implementation
168
Figure 62: Transformer Losses
168
Thermal Overload Bias Current
169
The Thermal Model
170
Top Oil Temperature Caculations
170
Hotspot Caculations
170
Thermal State Measurement
171
Application Notes
171
Alstom Recommendations
171
IEEE Recommendations
171
Data Provided by Transformer Manufacturers
172
Loss of Life Statistics
174
Loss of Life Implementation
174
Loss of Life Calculations
174
Application Notes
176
LOL Setting Guidelines
176
Example
176
Through Fault Monitoring
178
Through Fault Monitoring Implementation
178
Through Fault Monitoring Logic
179
Application Notes
179
TFM Setting Guidelines
179
Figure 63: Through-Fault Alarm Logic
179
Through Fault Monitoring
179
Figure 64: P645 Used to Protect an Autotransformer with Loaded Delta Winding
180
RTD Protection
181
RTD Protection Implementation
181
Figure 65: Connection for RTD Thermal Probes
181
RTD Logic
182
Application Notes
182
Setting Guidelines for RTD Protection
182
Figure 66: RTD Logic
182
CLIO Protection
183
Current Loop Input Implementation
183
Figure 67: Current Loop Input Ranges
184
Current Loop Input Logic
185
CLO Implementation
185
Figure 68: Current Loop Input Logic
185
Figure 69: Current Loop Output Ranges
186
Application Notes
187
CLI Setting Guidelines
187
CLO Setting Guidelines
187
Chapter 8 Restricted Earth Fault Protection
189
Chapter Overview
191
REF Protection Principles
192
Figure 70: REF Protection for Delta Side
192
Figure 71: REF Protection for Star Side
192
Resistance-Earthed Star Windings
193
Solidly-Earthed Star Windings
193
Figure 72: REF Protection for Resistance-Earthed Systems
193
Figure 73: REF Protection for Solidly Earthed System
193
Through Fault Stability
194
Restricted Earth Fault Types
194
Low Impedance REF Principle
194
High Impedance REF Principle
195
Figure 74: Low Impedance REF Connection
195
Figure 75: Three-Slope REF Bias Characteristic
195
Figure 76: High Impedance REF Principle
196
Figure 77: High Impedance REF Connection
196
Restricted Earth Fault Protection Implementation
197
Enabling REF Protection
197
Selecting the Current Inputs
197
Low Impedance REF
198
Setting the Bias Characteristic
198
Figure 78: REF Bias Characteristic
198
Delayed Bias
199
Transient Bias
199
Restricted Earth Fault Logic
199
High Impedance REF
199
Figure 79: Low Impedance Restricted Earth Fault Logic
199
High Impedance REF Calculation Principles
200
Second Harmonic Blocking
201
REF 2Nd Harmonic Blocking Logic
201
Figure 80: REF 2Nd Harmonic Blocking Logic
201
Application Notes
202
Star Winding Resistance Earthed
202
Figure 81: Star Winding, Resistance Earthed
202
Figure 82: Percentage of Winding Protected
202
Low Impedance REF Protection Application
203
Setting Guidelines for Biased Operation
203
Low Impedance REF Scaling Factor
203
Parameter Calculations
203
Figure 83: Low Impedance REF Scaling Factor
203
Dual CB Application with Different Phase CT Ratios
204
Figure 84: Low-Z REF for Dual CB Application with Different Phase CT Ratios
204
Dual CB Application with same Phase CT Ratios
205
CT Requirements - Low Impedance REF
205
Figure 85: Low-Z REF for Dual CB Application with same Phase CT Ratios
205
High Impedance REF Protection Application
207
High Impedance REF Operating Modes
207
Figure 86: Hi-Z REF Protection for a Grounded Star Winding
208
Figure 87: Hi-Z REF Protection for a Delta Winding
208
Setting Guidelines for High Impedance Operation
209
Figure 88: Hi-Z REF Protection for Autotransformer Configuration
209
Figure 89: High Impedance REF for the LV Winding
209
Use of Metrosil Non-Linear Resistors
211
CT Requirements - High Impedance REF
213
Figure 90: High Impedance REF CT Requirement
214
Chapter 9 Current Protection Functions
215
Chapter Overview
217
Overcurrent Protection Principles
218
IDMT Characteristics
218
IEC 60255 IDMT Curves
219
European Standards
220
Figure 91: IEC 60255 IDMT Curves
220
North American Standards
222
Differences between the North American and European Standards
223
Principles of Implementation
223
Figure 92: Principle of Protection Function Implementation
223
Timer Hold Facility
224
Magnetising Inrush Restraint
224
Figure 93: Magnetising Inrush Phenomenon
225
Phase Overcurrent Protection
226
Phase Overcurrent Protection for Power Transformers
226
Phase Overcurrent Protection Implementation
226
Selecting the Current Inputs
227
Non-Directional Overcurrent Logic
228
Figure 94: Non-Directional Overcurrent Logic Diagram
228
Directional Element
229
Implementing Directionalisation
229
Directional Overcurrent Logic
231
Application Notes
231
Setting Guidelines
231
Figure 95: Directional Overcurrent Logic Diagram
231
Parallel Feeders
233
Figure 96: Typical Distribution System Using Parallel Transformers
233
Voltage Dependent Overcurrent Element
234
Current Setting Threshold Selection
234
VCO Implementation
234
Figure 97: Selecting the Current Threshold Setting
234
Figure 98: Modification of Current Pickup Level for Voltage Controlled Overcurrent Protection
235
Negative Sequence Overcurrent Protection
236
NPSOC Protection Implementation
236
Non-Directional NPSOC Logic
236
Figure 99: Negative Sequence Overcurrent Logic - Non-Directional Operation
236
Directional Element
237
Directional NPSOC Logic
237
Figure 100: Negative Phase Equence Overcurrent Logic - Directional Operation
237
Application Notes
238
Setting Guidelines (General)
238
Setting Guidelines (Current Threshold)
238
Setting Guidelines (Time Delay)
238
Setting Guidelines (Directional Element)
238
Earth Fault Protection
240
Earth Fault Protection Elements
240
Non-Directional Earth Fault Logic
241
IDG Curve
241
Figure 101: Non-Directional EF Logic (Single Stage)
241
Directional Element
242
Residual Voltage Polarisation
242
Figure 102: IDG Characteristic
242
Negative Sequence Polarisation
243
Figure 103: Directional EF Logic with Neutral Voltage Polarization (Single Stage)
243
Application Notes
244
Setting Guidelines (Non-Directional)
244
Figure 104: Directional Earth Fault Logic with Negative Phase Sequence Polarisation
244
Setting Guidelines (Directional Element)
245
Second Harmonic Blocking
246
Second Harmonic Blocking Implementation
246
Second Harmonic Blocking Logic
247
EF Second Harmonic Blocking Logic
247
Application Notes
247
Setting Guidelines
247
Figure 105: Phase Overcurrent 2Nd Harmonic Blocking Logic
247
Figure 106: Earth Fault 2Nd Harmonic Blocking Logic
247
Chapter 10 CB Fail Protection
249
Chapter Overview
251
Circuit Breaker Fail Protection
252
Circuit Breaker Fail Implementation
253
Circuit Breaker Fail Timers
253
Zero Crossing Detection
254
Circuit Breaker Fail Logic
255
Figure 107: Circuit Breaker Fail Logic - Part 1
255
Figure 108: Circuit Breaker Fail Logic - Part 2
256
Application Notes
257
Reset Mechanisms for CB Fail Timers
257
Setting Guidelines (CB Fail Timer)
257
Setting Guidelines (Undercurrent)
258
Figure 109: CB Fail Timing
258
Chapter 11 Voltage Protection Functions
259
Chapter Overview
261
Undervoltage Protection
262
Undervoltage Protection Implementation
262
Undervoltage Protection Logic
263
Figure 110: Undervoltage - Single and Three Phase Tripping Mode (Single Stage)
263
Application Notes
264
Undervoltage Setting Guidelines
264
Overvoltage Protection
265
Overvoltage Protection Implementation
265
Overvoltage Protection Logic
266
Application Notes
266
Overvoltage Setting Guidelines
266
Figure 111: Overvoltage - Single and Three Phase Tripping Mode (Single Stage)
266
Residual Overvoltage Protection
268
Residual Overvoltage Protection Implementation
268
Residual Overvoltage Logic
269
Application Notes
269
Calculation for Solidly Earthed Systems
269
Figure 112: Residual Overvoltage Logic
269
Calculation for Impedance Earthed Systems
270
Figure 113: Residual Voltage for a Solidly Earthed System
270
Setting Guidelines
271
Figure 114: Residual Voltage for an Impedance Earthed System
271
Negative Sequence Overvoltage Protection
272
Negative Sequence Overvoltage Implementation
272
Negative Sequence Overvoltage Logic
272
Application Notes
272
Setting Guidelines
272
Figure 115: Negative Sequence Overvoltage Logic
272
Chapter 12 Frequency Protection Functions
275
Chapter Overview
277
Overfluxing Protection
278
Overfluxing Protection Implementation
278
Time-Delayed Overfluxing Protection
279
Figure 116: Variable Time Overfluxing Protection Characteristic
279
5Th Harmonic Blocking
280
Overfluxing Protection Logic
280
Figure 117: Overfluxing Reset Characteristic
280
Figure 118: 5Th Harmonic Blocking Time Delay in PSL
280
Application Notes
281
Overfluxing Protection Setting Guidelines
281
Figure 119: Overfluxing Protection Logic
281
Figure 120: Multi-Stage Overfluxing Characteristic
282
Figure 121: Scheme Logic for Multi-Stage Overfluxing Characteristic
282
Frequency Protection
283
Underfrequency Protection
283
Underfrequency Protection Implementation
283
Underfrequency Protection Logic
283
Figure 122: Underfrequency Logic (Single Stage)
283
Application Notes
284
Overfrequency Protection
284
Overfrequency Protection Implementation
284
Overfrequency Protection Logic
284
Figure 123: Overfrequency Logic (Single Stage)
284
Application Notes
285
Chapter 13 Monitoring and Control
287
Chapter Overview
289
Event Records
290
Event Types
290
Opto-Input Events
291
Contact Events
291
Alarm Events
291
Fault Record Events
295
Maintenance Events
295
Figure 124: Fault Recorder Stop Conditions
295
Protection Events
296
Security Events
296
Platform Events
296
Disturbance Recorder
297
Measurements
298
Measured Quantities
298
Measured and Calculated Currents
298
Measured and Calculated Voltages
298
Power and Energy Quantities
298
Demand Values
299
Other Measurements
299
Measurement Setup
299
Opto-Input Time Stamping
299
Current Input Exclusion Function
300
Current Input Exclusion Logic
300
Application Notes
300
Current Input Exclusion Example
300
Figure 125: CT Exclusion Logic
300
Figure 126: CT Input Exclusion - 1.5 CB Application
301
Figure 127: CT Input Exclusion - Auxiliary Contact Connection
301
Pole Dead Function
302
Pole Dead Function Implementation
302
Pole Dead Logic
303
Figure 128: Pole Dead Logic - P642
303
CB Status Indication
304
Figure 129: Pole Dead Logic - P643 and P645
304
Figure 130: Forcing CB Closed Signals
305
Chapter 14 Supervision
307
Chapter Overview
309
Voltage Transformer Supervision
310
Loss of One or Two Phase Voltages
310
Loss of All Three Phase Voltages
310
Absence of All Three Phase Voltages on Line Energisation
310
VTS Implementation
311
VTS Logic
312
Figure 131: VTS Logic (P642 with 2 Single-Phase Vts)
312
Figure 132: VTS Logic (P643 and P645 with 3-Phase Vts)
313
Current Transformer Supervision
315
CTS Implementation
315
Figure 133: CTS Restraint Region Increase
315
CTS Logic
316
Figure 134: CTS Logic Diagram
316
Application Notes
317
Setting Guidelines
317
Trip Circuit Supervision
318
Trip Circuit Supervision Scheme
318
Resistor Values
318
Figure 135: TCS Scheme 1
318
Psl for Tcs Scheme 1
319
Trip Circuit Supervision Scheme
319
Figure 136: PSL for TCS Scheme 1
319
Resistor Values
320
Psl for Tcs Scheme 2
320
Trip Circuit Supervision Scheme
320
Figure 138: PSL for TCS Scheme 2
320
Figure 139: TCS Scheme 3
320
Resistor Values
321
Psl for Tcs Scheme 3
321
Figure 140: PSL for TCS Scheme 3
321
Chapter 15 Digital I/O and PSL Configuration
323
Chapter Overview
325
Configuring Digital Inputs and Outputs
326
Scheme Logic
327
Figure 141: Scheme Logic Interfaces
327
PSL Editor
328
PSL Schemes
328
PSL Scheme Version Control
328
Configuring the Opto-Inputs
329
Assigning the Output Relays
330
Fixed Function Leds
331
Trip LED Logic
331
Figure 142: Trip LED Logic
331
Configuring Programmable Leds
332
Function Keys
334
Control Inputs
335
Chapter 16 Communications
337
Chapter Overview
339
Communication Interfaces
340
Serial Communication
341
EIA(RS)232 Bus
341
EIA(RS)485 Bus
341
EIA(RS)485 Biasing Requirements
342
K-Bus
342
Figure 143: RS485 Biasing Circuit
342
Figure 144: Remote Communication Using K-Bus
343
Standard Ethernet Communication
344
Hot-Standby Ethernet Failover
344
Redundant Ethernet Communication
345
Supported Protocols
345
Parallel Redundancy Protocol
346
Figure 145: IED Attached to Separate Lans
346
Rapid Spanning Tree Protocol
347
Self Healing Protocol
347
Figure 146: IED Attached to Redundant Ethernet Star or Ring Circuit
347
Figure 147: IED, Bay Computer and Ethernet Switch with Self Healing Ring Facilities
348
Figure 148: Redundant Ethernet Ring Architecture with IED, Bay Computer and Ethernet Switches
348
Figure 149: Redundant Ethernet Ring Architecture with IED, Bay Computer and Ethernet Switches
348
Dual Homing Protocol
349
Figure 150: Dual Homing Mechanism
349
Redundant Ethernet Configuration
350
Figure 151: Application of Dual Homing Star at Substation Level
350
Figure 152: IED and REB Switch IP Address Configuration
351
Figure 153: DIP Switches for Setting IP Address
351
Setting the NIC IP Address
352
Setting the Switch IP Address
352
Data Protocols
353
Courier
353
Physical Connection and Link Layer
353
Courier Database
354
Settings Categories
354
Setting Changes
354
Event Extraction
354
Disturbance Record Extraction
356
Programmable Scheme Logic Settings
356
Time Synchronisation
356
Courier Configuration
357
Physical Connection and Link Layer
358
Iec 60870-5-103
358
Initialisation
359
Time Synchronisation
359
Spontaneous Events
359
General Interrogation (GI)
359
Cyclic Measurements
359
Commands
359
Test Mode
360
Disturbance Records
360
Command/Monitor Blocking
360
IEC 60870-5-103 Configuration
360
Dnp
361
Physical Connection and Link Layer
362
Object 1 Binary Inputs
362
Object 10 Binary Outputs
362
Object 20 Binary Counters
363
Object 30 Analogue Input
363
Figure 154: Control Input Behaviour
363
Object 40 Analogue Output
364
Object 50 Time Synchronisation
364
DNP3 Device Profile
364
DNP3 Configuration
372
Modbus
373
Physical Connection and Link Layer
374
MODBUS Functions
374
Response Codes
374
Register Mapping
375
Event Extraction
375
Disturbance Record Extraction
376
Figure 155: Manual Selection of a Disturbance Record
379
Figure 156: Automatic Selection of Disturbance Record - Method 1
380
Figure 157: Automatic Selection of Disturbance Record - Method 2
381
Figure 158: Configuration File Extraction
382
Figure 159: Data File Extraction
383
Setting Changes
384
Password Protection
384
Protection and Disturbance Recorder Settings
384
Time Synchronisation
385
Power and Energy Measurement Data Formats
386
MODBUS Configuration
387
Iec 61850
388
Benefits of IEC 61850
388
IEC 61850 Interoperability
389
The IEC 61850 Data Model
389
Figure 160: Data Model Layers in IEC61850
389
IEC 61850 in Micom Ieds
390
IEC 61850 Data Model Implementation
390
IEC 61850 Communication Services Implementation
390
IEC 61850 Peer-To-Peer (GOOSE) Communications
391
Mapping GOOSE Messages to Virtual Inputs
391
Ethernet Functionality
391
IEC 61850 Configuration
391
Read Only Mode
393
Courier Protocol Blocking
393
IEC 61850 Protocol Blocking
394
Read-Only Settings
394
Read-Only DDB Signals
394
Time Synchronisation
395
Demodulated IRIG-B
395
IRIG-B Implementation
395
Figure 161: GPS Satellite Timing Signal
395
Sntp
396
Time Synchronsiation Using the Communication Protocols
396
Chapter 17 Cyber-Security
397
Overview
399
The Need for Cyber-Security
400
Standards
401
NERC Compliance
401
Cip 002
402
Cip 007
403
Ieee 1686-2007
403
Cyber-Security Implementation
405
NERC-Compliant Display
405
Four-Level Access
406
Figure 162: Default Display Navigation
406
Blank Passwords
407
Password Rules
407
Access Level Ddbs
408
Enhanced Password Security
408
Password Strengthening
408
Password Validation
408
Password Blocking
409
Password Recovery
410
Password Encryption
411
Disabling Physical Ports
411
Disabling Logical Ports
411
Security Events Management
412
Logging out
414
Chapter 18 Installation
415
Chapter Overview
417
Handling the Goods
418
Receipt of the Goods
418
Unpacking the Goods
418
Storing the Goods
418
Dismantling the Goods
418
Mounting the Device
419
Flush Panel Mounting
419
Figure 163: Location of Battery Isolation Strip
419
Rack Mounting
420
Figure 164: Rack Mounting of Products
420
Cables and Connectors
422
Terminal Blocks
422
Figure 165: Terminal Block Types
422
Power Supply Connections
423
Earth Connnection
423
Current Transformers
423
Voltage Transformer Connections
424
Watchdog Connections
424
EIA(RS)485 and K-Bus Connections
424
IRIG-B Connection
424
Opto-Input Connections
424
Output Relay Connections
424
Ethernet Metallic Connections
425
Ethernet Fibre Connections
425
RS232 Connection
425
Download/Monitor Port
425
GPS Fibre Connection
425
Fibre Communication Connections
425
RTD Connections
426
CLIO Connections
427
Case Dimensions
428
Case Dimensions 40TE
428
Figure 166: 40TE Case Dimensions
428
Case Dimensions 60TE
429
Figure 167: 60TE Case Dimensions
429
Case Dimensions 80TE
430
Figure 168: 80TE Case Dimensions
430
Chapter 19 Commissioning Instructions
431
Chapter Overview
433
General Guidelines
434
Commissioning Test Menu
435
Opto I/P Status Cell (Opto-Input Status)
435
Relay O/P Status Cell (Relay Output Status)
435
Test Mode Cell
435
Test Pattern Cell
436
Contact Test Cell
436
Test Leds Cell
436
Red and Green LED Status Cells
436
PSL Verificiation
436
Test Port Status Cell
436
Monitor Bit 1 to 8 Cells
436
Using a Monitor Port Test Box
437
Commissioning Equipment
438
Recommended Commissioning Equipment
438
Essential Commissioning Equipment
438
Advisory Test Equipment
439
Product Checks
440
Product Checks with the IED De-Energised
440
Visual Inspection
441
Current Transformer Shorting Contacts
441
Insulation
441
External Wiring
441
Watchdog Contacts
442
Power Supply
442
Product Checks with the IED Energised
442
Test LCD
443
Date and Time
443
Test Leds
444
Test Alarm and Out-Of-Service Leds
444
Test Trip LED
444
Test User-Programmable Leds
444
Test Opto-Inputs
444
Test Output Relays
444
RTD Inputs
445
Current Loop Outputs
445
Current Loop Inputs
445
Test Serial Communication Port RP1
446
Figure 169: RP1 Physical Connection
446
Test Serial Communication Port RP2
447
Figure 170: Remote Communication Using K-Bus
447
Test Ethernet Communication
448
Secondary Injection Tests
448
Test Current Inputs
448
Test Voltage Inputs
449
Setting Checks
450
Apply Application-Specific Settings
450
Transferring Settings from a Settings File
450
Entering Settings Using the HMI
450
Checking the Differential Element
452
Using the Omicron Advanced Module
452
Figure 171: Operating Characteristic Diagram
453
Figure 172: Trip Time Test Plane
453
Figure 173: Harmonic Restraint Test Plane
454
Protection Timing Checks
455
Bypassing the All Pole Dead Blocking Condition
455
Overcurrent Check
455
Connecting the Test Circuit
455
Performing the Test
455
Check the Operating Time
455
Onload Checks
457
Confirm Current Connections
457
Confirm Voltage Connections
457
On-Load Directional Test
458
Final Checks
459
Chapter 20 Maintenance and Troubleshooting
461
Chapter Overview
463
Maintenance
464
Maintenance Checks
464
Alarms
464
Opto-Isolators
464
Output Relays
464
Measurement Accuracy
464
Replacing the Device
465
Repairing the Device
466
Removing the Front Panel
466
Figure 174: Possible Terminal Block Types
466
Replacing Pcbs
467
Replacing the Main Processor Board
467
Replacement of Communications Boards
468
Figure 175: Front Panel Assembly
468
Replacement of the Input Module
469
Replacement of the Power Supply Board
469
Replacement of the I/O Boards
470
Recalibration
470
Changing the Battery
470
Post Modification Tests
471
Battery Disposal
471
Cleaning
471
Troubleshooting
472
Self-Diagnostic Software
472
Power-Up Errors
472
Error Message or Code on Power-Up
472
Out of Service LED on at Power-Up
473
Error Code During Operation
474
Backup Battery
474
Mal-Operation During Testing
474
Failure of Output Contacts
474
Failure of Opto-Inputs
474
Incorrect Analogue Signals
475
PSL Editor Troubleshooting
475
Diagram Reconstruction
475
PSL Version Check
475
Repair and Modification Procedure
476
Chapter 21 Technical Specifications
477
Chapter Overview
479
Interfaces
480
Front Serial Port
480
Download/Monitor Port
480
Rear Serial Port
480
Fibre Rear Serial Port
480
IRIG-B (Demodulated)
481
IRIG-B (Modulated)
481
Rear Ethernet Port Copper
481
Rear Serial Port 2
481
Rear Ethernet Port Fibre
482
100 Base Fx Receiver Characteristics
482
100 Base Fx Transmitter Characteristics
482
Performance of Transformer Differential Protection and Monitoring Functions
483
Transformer Differential Protection
483
Matching Factors
483
Circuitry Fault Alarm
483
Through Fault Monitoring
484
Thermal Overload
484
Low Impedance Restricted Earth Fault
484
High Impedance Restricted Earth Fault
484
Performance of Current Protection Functions
485
Transient Overreach and Overshoot
485
Three-Phase Overcurrent Protection
485
Three-Phase Overcurrent Directional Parameters
485
Voltage Dependent Overcurrent Protection
485
Earth Fault Protection
486
Earth Fault Directional Parameters
486
Negative Sequence Overcurrent Protection
486
NPSOC Directional Parameters
486
Circuit Breaker Fail Protection
487
Performance of Voltage Protection Functions
488
Undervoltage Protection (P643/5)
488
Overvoltage Protection
488
Residual Overvoltage Protection (P643/5)
488
Negative Sequence Voltage Protection
488
Performance of Frequency Protection Functions
489
Overfrequency Protection
489
Underfrequency Protection
489
Overfluxing Protection
489
Performance of Monitoring and Control Functions
490
Voltage Transformer Supervision
490
Current Transformer Supervision
490
Pole Dead Protection
490
PSL Timers
491
Measurements and Recording
492
General
492
Disturbance Records
492
Event, Fault and Maintenance Records
492
Current Loop Inputs/Outputs
492
Standards Compliance
494
EMC Compliance: 2004/108/EC
494
Product Safety: 2006/95/EC
494
R&TTE Compliance
494
UL/CUL Compliance
494
ATEX Compliance
494
IDMT Standards
495
Mechanical Specifications
496
Physical Parameters
496
Enclosure Protection
496
Mechanical Robustness
496
Transit Packaging Performance
496
Ratings
497
AC Measuring Inputs
497
Current Transformer Inputs
497
Voltage Transformer Inputs
497
Power Supply
498
Auxiliary Supply Voltage
498
Nominal Burden
498
Power Supply Interruption
498
Battery Backup
499
Input / Output Connections
500
Isolated Digital Inputs
500
Nominal Pickup and Reset Thresholds
500
Standard Output Contacts
500
High Break Output Contacts
501
Watchdog Contacts
501
Environmental Conditions
502
Ambient Temperature Range
502
Temperature Endurance Test
502
Ambient Humidity Range
502
Corrosive Environments
502
Type Tests
503
Insulation
503
Creepage Distances and Clearances
503
High Voltage (Dielectric) Withstand
503
Impulse Voltage Withstand Test
503
Electromagnetic Compatibility
504
Mhz Burst High Frequency Disturbance Test
504
Damped Oscillatory Test
504
Immunity to Electrostatic Discharge
504
Electrical Fast Transient or Burst Requirements
504
Surge Withstand Capability
504
Surge Immunity Test
505
Immunity to Radiated Electromagnetic Energy
505
Radiated Immunity from Digital Communications
505
Radiated Immunity from Digital Radio Telephones
505
Immunity to Conducted Disturbances Induced by Radio Frequency Fields
505
Magnetic Field Immunity
506
Conducted Emissions
506
Radiated Emissions
506
Power Frequency
506
Appendix A Ordering Options
507
Appendix B Settings and Signals
509
Appendix C Wiring Diagrams
515
5
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GE P642 Specifications
General
Brand
GE
Model
P642
Category
Relays
Language
English
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