percent of the global parameter UBase. To avoid oscillations of the output START
signal, a hysteresis has been included.
START
START
TRIP
Start
&
Trip
Output
Logic
Definite Time Delay
TimeDlyOperate
BLOCK
IEC09000033-1.vsd
Frequency Comparator
f > StartFrequency
TRIP
BLKDMAGN
BLOCK
OR
freqNotValid
IEC09000033 V1 EN
Figure 152: Schematic design of overfrequency protection SAPTOF
10.2.7.2 Time delay
The time delay for SAPTOF is a settable definite time delay, specified by the setting
tDelay.
If the START condition frequency ceases during the delay time, and is not fulfilled
again within a defined reset time, the START output is reset.
10.2.7.3 Blocking
It is possible to block Over frequency protection (SAPTOF) completely, by binary
input signals or by parameter settings, where:
BLOCK:
blocks all outputs
If the measured voltage level decreases below the setting of MinValFreqMeas in the
preprocessing function both the START and the TRIP outputs are blocked.
10.2.7.4 Design
The design of overfrequency protection SAPTOF is schematically described in
figure 152.
1MRK 502 048-UEN A Section 10
Frequency protection
301
Technical manual
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