Contention between TCOR Write and Compare-Match: If a compare-match occurs during the
T3 state of a write cycle to TCORA or TCORB, the write takes precedence and the compare-
match signal is inhibited.
Figure 11-11 shows this type of contention.
Contention between Compare-Match A and Compare-Match B: If identical time constants
are written in TCORA and TCORB, causing compare-match A and B to occur simultaneously,
any conflict between the output selections for compare-match A and B is resolved by following
the priority order in table 11-4.
TCNT address
N N + 1
NM
Write cycle: CPU writes to TCORA
or TCORB
T
1 T2 T3
TCOR write
data
Inhibited
Internal address
bus
ø
Internal write
signal
TCNT
TCORA or
TCORB
Compare-match
A or B signal
Figure 11-11 Contention between TCOR Write and Compare-Match
222
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