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H8/500 Series
Hitachi H8/500 Series User Manual
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Table of Contents
Table of Contents
3
Section 1 Overview
22
Features
22
Addressing Modes
23
Block Diagram
25
Pin Arrangements and Functions
26
Pin Arrangement
26
Pin Arrangement (CP-84, Top View)
26
Section 2 MCU Operating Modes and Address Space
43
Overview
43
Operating Modes
43
Mode Descriptions
44
Address Space Map
45
Page Segmentation
45
Address Space in each Mode
46
Address Allocations
47
Mode Control Register (MDCR)
49
Mode Control Register
49
Section 3 CPU
50
Overview
50
Features
50
Address Space
51
CPU Operating Modes
51
Register Configuration
52
Registers in the CPU
52
CPU Register Descriptions
53
General Registers
53
Stack Pointer
53
Control Registers
54
Interrupt Mask Levels
55
Interrupt Mask Bits after an Interrupt Is Accepted
55
Combinations of Page Registers with Other Registers
57
Short Absolute Addressing Mode and Base Register
58
Initial Register Values
59
Data Formats
60
Data Formats in General Registers
60
Initial Values of Registers
60
Data Formats in Memory
61
General Register Data Formats
61
Data Formats in Memory
62
Instructions
63
Basic Instruction Formats
63
Data Formats on the Stack
63
Addressing Modes
64
Effective Address Calculation
66
Instruction Set
69
Overview
69
Instruction Classification
69
Data Transfer Instructions
71
Arithmetic Instructions
72
Logic Operations
73
Logic Operation Instructions
73
Shift Operations
74
Shift Instructions
74
Bit Manipulations
75
Bit-Manipulation Instructions
75
Branching Instructions
76
System Control Instructions
78
Operating Modes
81
Minimum Mode
81
Short-Format Instructions and Equivalent General Formats
81
Maximum Mode
82
Basic Operational Timing
82
Overview
82
On-Chip Memory Access Cycle
83
On-Chip Memory Access Timing
83
Pin States During On-Chip Memory Access
84
Pin States During Access to On-Chip Memory
84
Register Field Access Cycle (Addresses H'FF80 to H'FFFF)
85
Register Field Access Timing
85
Pin States During Register Field Access (Addresses H'FF80 to H'FFFF)
86
Pin States During Register Field Access
86
External Access Cycle
87
CPU States
88
Overview
88
Operating States
89
Power-Down State
89
Program Execution State
90
Exception-Handling State
90
State Transitions
90
Bus-Released State
91
Bus-Right Release Cycle (During On-Chip Memory Access Cycle)
92
Bus-Right Release Cycle (During External Access Cycle)
93
Bus-Right Release Cycle (During Internal CPU Operation)
94
Reset State
96
Power-Down State
96
Programming Notes
97
Restriction on Address Location
97
Note on MULXU Instruction
98
Section 4 Exception Handling
100
Overview
100
Types of Exception Handling and Their Priority
100
Hardware Exception-Handling Sequence
101
Exception Factors and Vector Table
101
Types of Factors Causing Exception Handling
102
Exception Vector Table
103
Reset
104
Overview
104
Reset Sequence
104
Stack Pointer Initialization
105
Reset Vector
105
Reset Sequence (Minimum Mode, On-Chip Memory)
106
Reset Sequence (Maximum Mode, External Memory)
107
Address Error
108
Illegal Instruction Prefetch
108
Word Data Access at Odd Address
108
Off-Chip Address Access in Single-Chip Mode
108
Trace
109
Interrupts
109
Interrupt Sources (and Number of Interrupt Types)
110
Invalid Instruction
111
Trap Instructions and Zero Divide
111
Cases in Which Exception Handling Is Deferred
111
Instructions that Disable Interrupts
111
Disabling of Exceptions Immediately after a Reset
112
Disabling of Interrupts after a Data Transfer Cycle
112
Stack Status after Completion of Exception Handling
113
Stack after Exception Handling Sequence
113
PC Value Pushed on Stack for Trace
115
Interrupts, Trap Instructions, and Zero Divide Exceptions
115
Instruction Exceptions
115
Notes on Use of the Stack
115
Section 5 Interrupt Controller
116
Overview
116
Features
116
Block Diagram
117
Interrupt Controller Block Diagram
117
Register Configuration
118
Interrupt Types
118
External Interrupts
118
Interrupt Controller Registers
118
Internal Interrupts
120
Interrupt Vector Table
120
Interrupts, Vectors, and Priorities
121
Register Descriptions
122
Interrupt Priority Registers a to D (IPRA to IPRD)
122
Assignment of Interrupt Priority Registers
122
Timing of Priority Setting
123
Interrupt Handling Sequence
123
Interrupt Handling Flow
123
Interrupt Handling Flowchart
125
Stack Status after Interrupt Handling Sequence
126
Timing of Interrupt Exception-Handling Sequence
127
Interrupts During Operation of the Data Transfer Controller
127
Interrupt Sequence (Minimum Mode, On-Chip Memory)
128
Interrupt Sequence (Maximum Mode, External Memory)
129
Interrupt Response Time
130
Number of States before Interrupt Service
130
Section 6 Data Transfer Controller
131
Overview
131
Features
131
Block Diagram
131
Register Configuration
132
Data Transfer Mode Register (DTMR)
132
Block Diagram of Data Transfer Controller
132
Internal Control Registers of the DTC
132
Data Transfer Enable Registers
133
Data Transfer Source Address Register (DTSR)
134
Data Transfer Destination Register (DTDR)
134
Data Transfer Count Register (DTCR)
134
Data Transfer Enable Registers a to D (DTEA to DTED)
135
Assignment of Data Transfer Enable Registers
135
Data Transfer Operation
136
Data Transfer Cycle
136
Flowchart of Data Transfer Cycle
137
DTC Vector Table
138
DTC Vector Table Entry
139
Addresses of DTC Vectors
139
Location of Register Information in Memory
140
Length of Data Transfer Cycle
140
Order of Register Information
140
Number of States Per Data Transfer
141
Procedure for Using the DTC
142
Number of States before Interrupt Service
142
Example
143
DTC Control Register Information Set in RAM
143
Use of DTC to Receive Data Via Serial Communication Interface
144
Section 7 Wait-State Controller
145
Overview
145
Features
145
Block Diagram
146
Register Configuration
146
Block Diagram of Wait-State Controller
146
Wait-State Control Register
147
Operation in each Wait Mode
148
Programmable Wait Mode
148
Wait Modes
148
Pin Wait Mode
149
Programmable Wait Mode
149
Pin Wait Mode
150
Pin Auto-Wait Mode
151
Section 8 Clock Pulse Generator
152
Overview
152
Block Diagram
152
Oscillator Circuit
152
Block Diagram of Clock Pulse Generator
152
Connection of Crystal Oscillator (Example)
153
Crystal Oscillator Equivalent Circuit
153
External Crystal Parameters
153
Notes on Board Design Around External Crystal
154
External Clock Input (Example)
154
System Clock Divider
155
Phase Relationship of Ø Clock and E Clock
155
Section 9 I/O Ports
156
Overview
156
Input/Output Port Summary
157
Port 1
159
Overview
159
Port 1 Registers
159
Pin Functions
159
And P1
160
Pin Functions in each Mode
162
Port 1 Pin Functions in Expanded Modes
162
Port 1 Pin Functions in Single-Chip Modes
164
Port 2
166
Port 2 Registers
166
Pin Functions in each Mode
167
Port 2 Pin Functions in Expanded Modes
167
Port 3
168
Overview
168
Port 2 Pin Functions in Single-Chip Mode
168
Port 3 Registers
169
Pin Functions in each Mode
170
Port 3 Pin Functions in Expanded Modes
170
Port 3 Pin Functions in Single-Chip Mode
171
Port 4
172
Port 4 Registers
172
Pin Functions in each Mode
173
Port 4 Pin Functions in Expanded Modes
173
Overview
174
Port 4 Pin Functions in Single-Chip Mode
174
Port 5 Registers
175
Pin Functions in each Mode
176
Port 5 Pin Functions in Single-Chip Mode
177
Built-In MOS Pull
178
Overview
180
Port 6 Registers
181
Port 7
184
Overview
184
Port 7 Registers
185
Pin Functions
186
Port 7 Pin Functions
187
Port 8
189
Overview
189
Port 8 Registers
189
Port 9
190
Overview
190
Port 9 Registers
190
Port 9 Pin Functions
192
Pin Functions
193
Section 10 16-Bit Free-Running Timers
194
Overview
194
Features
194
Block Diagram
195
Block Diagram of 16-Bit Free-Running Timer
195
Input and Output Pins
196
Input and Output Pins of Free-Running Timer Module
196
Register Configuration
197
Register Descriptions
198
Free-Running Counter (FRC)-H'FF92, H'FFA2, H'FFB2
198
Input Capture Register (ICR)-H'FF98, H'FFA8, H'FFB8
199
Timer Control Register (TCR)
200
Timer Control/Status Register (TCSR)
202
CPU Interface
205
Operation
207
FRC Incrementation Timing
207
Output Compare Timing
208
Increment Timing for External Clock Input
208
Setting of Output Compare Flags
209
Timing of Output Compare
209
Input Capture Timing
210
Clearing of FRC by Compare-Match
210
Input Capture Timing (Usual Case)
210
Input Capture Timing (1-State Delay)
211
Setting of Input Capture Flag
211
Setting of FRC Overflow Flag (OVF)
212
CPU Interrupts and DTC Interrupts
212
Setting of Overflow Flag (OVF)
212
Free-Running Timer Interrupts
212
Synchronization of Free-Running Timers 1
213
Synchronization after a Reset
213
Synchronization by Writing to Frcs
213
Sample Application
217
Application Notes
217
Contention between OCR Write and Compare-Match
220
Effect of Changing Internal Clock Sources
221
Effect of Changing Internal Clock Sources
222
Section 11 8-Bit Timer
223
Overview
223
Features
223
Block Diagram
224
Block Diagram of 8-Bit Timer
224
Input and Output Pins
225
Register Configuration
225
Register Descriptions
225
Timer Counter (TCNT)-H'FFD4
225
Input and Output Pins of 8-Bit Timer
225
Time Constant Registers a and B
226
Timer Control Register (TCR)-H'FFD0
226
Timer Control/Status Register (TCSR)
228
Operation
230
TCNT Incrementation Timing
230
Compare Match Timing
231
Count Timing for External Clock Input
231
Setting of Compare-Match Flags
232
Timing of Timer Output
232
External Reset of TCNT
233
Timing of Compare-Match Clear
233
Timing of External Reset
233
Setting of TCNT Overflow Flag
234
CPU Interrupts and DTC Interrupts
234
Setting of Overflow Flag (OVF)
234
Sample Application
235
Example of Pulse Output
235
Application Notes
236
TCNT Write-Clear Contention
236
TCNT Write-Increment Contention
237
Contention between TCOR Write and Compare-Match
238
Priority Order of Timer Output
239
Section 12 PWM Timer
242
Overview
242
Features
242
Block Diagram
242
Input and Output Pins
243
Block Diagram of PWM Timer
243
Output Pins of PWM Timer Module
243
Register Configuration
244
Register Descriptions
244
Timer Counter (TCNT)-H'FFC2, H'FFC4, H'FFCA
244
PWM Timer Registers
244
Duty Register (DTR)-H'FFC1, H'FFC5, H'FFC9
245
Timer Control Register (TCR)-H'FFC0, H'FFC4, H'FFC8
245
Operation
247
PWM Timer Parameters for 10Mhz System Clock
247
PWM Timing
248
Application Notes
249
Section 13 Watchdog Timer
250
Overview
250
Features
250
Block Diagram
251
Register Configuration
251
Block Diagram of Timer Counter
251
Register Descriptions
252
Timer Counter TCNT-H'FFED
252
Timer Control/Status Register (TCSR)-H'FFEC (Read), H'FFED (Write)
252
Notes on Register Access
254
Writing to TCNT and TCSR
254
Operation
255
Watchdog Timer Mode
255
Read Addresses of TCNT and TCSR
255
Interval Timer Mode
256
Operation in Watchdog Timer Mode
256
Operation in Software Standby Mode
257
Operation in Interval Timer Mode
257
Setting of Overflow Flag
258
Application Notes
258
Setting of OVF Bit
258
TCNT Write-Increment Contention
259
Section 14 Serial Communication Interface
260
Overview
260
Features
260
Block Diagram
261
Block Diagram of Serial Communication Interface
261
Input and Output Pins
262
Register Configuration
262
Register Descriptions
262
Receive Shift Register (RSR)
262
SCI Input/Output Pins
262
SCI Registers
262
Receive Data Register (RDR)-H'FFDD
263
Transmit Shift Register (TSR)
263
Transmit Data Register (TDR)-H'FFDB
263
Serial Mode Register (SMR)-H'FFD8
264
Serial Control Register (SCR)-H'FFDA
266
Serial Status Register (SSR)-H'FFDC
268
Bit Rate Register (BRR)-H'FFD9
270
Examples of BRR Settings in Synchronous Mode
273
Operation
274
Overview
274
Communication Formats Used by SCI
274
SCI Clock Source Selection
274
Asynchronous Mode
275
Data Format in Asynchronous Mode
275
Phase Relationship between Clock Output and Transmit Data
276
Data Formats in Asynchronous Mode
276
Synchronous Mode
279
Receive Errors
279
Data Format in Synchronous Mode
280
CPU Interrupts and DTC Interrupts
283
Application Notes
284
SCI Interrupts
284
SSR Bit States and Data Transfer When Multiple Receive Errors Occur
285
Sampling Timing (Asynchronous Mode)
286
Section 15 A/D Converter
287
Overview
287
Features
287
Block Diagram
288
Block Diagram of A/D Converter
288
Input Pins
289
Register Configuration
289
A/D Input Pins
289
A/D Registers
289
Assignment of Data Registers to Analog Input Channels
290
A/D Control/Status Register (ADCSR)-H'FFE8
291
CPU Interface
293
Operation
294
Read Access to A/D Data Register (When Register Contains H'AA40)
294
Single Mode
295
A/D Operation in Single Mode (When Channel 1 Is Selected)
297
Scan Mode
298
A/D Operation in Scan Mode (When Channels 0 to 2 Are Selected)
300
Input Sampling Time and A/D Conversion Time
301
A/D Conversion Timing
302
A/D Conversion Time (Single Mode)
302
Interrupts and the Data Transfer Controller
303
Section 16 RAM
304
Overview
304
Block Diagram
304
Block Diagram of On-Chip RAM
304
Register Configuration
305
RAM Control Register (RAMCR)
305
Operation
305
Expanded Modes (Modes 1, 2, 3, and 4)
305
RAM Control Register
305
Single-Chip Mode (Mode 7)
306
Section 17 ROM
307
Overview
307
Block Diagram
307
ROM Usage in each MCU Mode
307
PROM Modes
308
PROM Mode Setup
308
Block Diagram of On-Chip ROM
308
Selection of PROM Mode
308
Socket Adapter Pin Arrangements and Memory Map
309
Socket Adapter
309
Socket Adapter Pin Arrangements
310
Programming
311
Writing and Verifying
311
Memory Map in PROM Mode
311
Selection of Sub-Modes in PROM Mode
311
High-Speed Programming Flowchart
312
CC = 6.0V ±0.25V, V Pp = 12.5V ±0.3V, V Ss = 0V
313
AC Characteristics (When VCC = 6.0V ±0.25V, VPP = 12.5V ±0.3V
313
Notes on Writing
314
PROM Write/Verify Timing
314
Reliability of Written Data
315
Recommended Screening Procedure
315
Erasing of Data
316
Handling of Windowed Packages
316
Erasing Conditions
316
Socket for 84-Pin LCC Package
317
Section 18 Power-Down State
318
Overview
318
Sleep Mode
319
Transition to Sleep Mode
319
Exit from Sleep Mode
319
Software Standby Mode
319
Transition to Software Standby Mode
319
Software Standby Control Register (SBYCR)
320
Software Standby Control Register
320
Exit from Software Standby Mode
321
Sample Application of Software Standby Mode
321
Application Notes
322
NMI Timing of Software Standby Mode (Application Example)
322
Hardware Standby Mode
323
Recovery from Hardware Standby Mode
323
Timing Sequence of Hardware Standby Mode
324
Hardware Standby Sequence
324
Section 19 E Clock Interface
325
Overview
325
Execution Cycle of Instruction Synchronized with E Clock in Expanded Modes
326
Execution Cycle of Instruction Synchronized with E Clock in Expanded Modes
327
Section 20 Electrical Specifications
328
Electrical Characteristics
328
DC Characteristics
328
Absolute Maximum Ratings
328
DC Characteristics
329
Allowable Output Current Sink Values
330
AC Characteristics
331
Example of Circuit for Driving a Darlington Transistor Pair
331
Example of Circuit for Driving an LED
331
Bus Timing
331
Control Signal Timing
333
Output Load Circuit
334
Timing Conditions of On-Chip Supporting Modules
334
A/D Converter Characteristics
335
MCU Operatinal Timing
335
Bus Timing
335
Control Signal Timing
335
Basic Bus Cycle (Without Wait States) in Expanded Modes
336
Basic Bus Cycle (with 1 Wait State) in Expanded Modes
337
Bus Cycle Synchronized with E Clock
338
Reset Input Timing
339
Interrupt Input Timing
339
NMI Pulse Width (for Recovery from Software Standby Mode)
339
Clock Timing
340
Bus Release State Timing
340
E Clock Timing
340
Clock Oscillator Stabilization Timing
341
I/O Port Timing
342
16-Bit Free-Running Timer Timing
343
Free-Running Timer Input/Output Timing
343
External Clock Input Timing for Free-Running Timers
343
8-Bit Timer Timing
344
Pulse Width Modulation Timer Timing
345
Serial Communication Interface Timing
345
PWM Timer Output Timing
345
SCI Input/Output Timing (Synchronous Mode)
345
Appendix A Instructions
346
Instruction Set
346
Instruction Codes
351
Operation Code Map
360
Instruction Execution Cycles
367
Calculation of Instruction Execution States
367
Tables of Instruction Execution Cycles
368
Appendix B Register Field
376
Register Addresses and Bit Names
376
Register Descriptions
381
A) Schematic Diagram of Port 1, Pin P1
416
B) Schematic Diagram of Port 1, Pin P1
416
C) Schematic Diagram of Port 1, Pin P1
417
D) Schematic Diagram of Port 1, Pin P1
418
E) Schematic Diagram of Port 1, Pin P1
419
Port 2 Port Read
422
Port 3 Port Read
423
Port 4 Port Read
424
Port 5 Port Read
425
Port 6 Port Read
426
And P9
433
And P9
434
C) Schematic Diagram of Port 9, Pin P9
435
D) Schematic Diagram of Port 9, Pin P9
436
E) Schematic Diagram of Port 9, Pin P9
437
Reset During Memory Access (Mode 1)
444
Reset During Memory Access (Mode 1)
445
Reset During Memory Access (Mode 2)
447
Reset During Memory Access (Mode 2)
448
Reset During Memory Access (Mode 3)
450
Reset During Memory Access (Mode 3)
451
Reset During Memory Access (Mode 4)
453
Reset During Memory Access (Mode 4)
454
Reset During Memory Access (Mode 7)
455
Reset During Memory Access (Mode 7)
456
Package Dimensions
458
Package Dimensions
459
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Hitachi H8/500 Series Specifications
General
Brand
Hitachi
Model
H8/500 Series
Category
Computer Hardware
Language
English
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