Section 18 Power-Down State
18.1 Overview
The H8/532 has a power-down state that greatly reduces power consumption by stopping the CPU
functions. The power-down state includes three modes:
1. Sleep mode— a software-triggered mode in which the CPU halts but the rest of
the chip remains active
2. Software standby mode— a software-triggered mode in which the entire chip is inactive
3. Hardware standby mode— a hardware-triggered mode in which the entire chip is inactive
The sleep mode and software standby mode are entered from the program execution state by
executing the SLEEP instruction under the conditions given in table 18-1. The hardware standby
mode is entered from any other state by a Low input at the STBY pin.
Table 18-1 lists the conditions for entering and leaving the power-down modes. It also indicates
the status of the CPU, on-chip supporting modules, etc., in each power-down mode.
Table 18-1 Power-Down State
Entering CPU Sup. I/O Exiting
Mode Procedure Clock CPU Reg’s. Mod’s. RAM Ports Methods
Sleep Execute Run Halt Held Run Held Held • Interrupt
mode SLEEP • RES Low
instruction • STBY Low
Soft- Set SSBY bit Halt Halt Held Halt Held Held • NMI
ware in SBYCR to and • RES Low
standby 1, then partly • STBY Low
mode execute SLEEP initialized
instruction*
Hard- Set STBY Halt Halt Not Halt Held High • STBY High,
ware pin to Low held and impe- then RES
standby level partly dance Low → High
mode initialized state
* The watchdog timer must also be stopped.
Notes: SBYCR Software standby control register
SSBY Software standby bit
307
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