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Hitachi H8/500 Series User Manual

Hitachi H8/500 Series
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Table 3-11 Arithmetic Instructions (cont)
Instruction Size Function
Arithmetic EXTS B (<bit 7> of <Rd>) (<bits 15 to 8> of <Rd>)
operations Converts byte data in a general register to word data by
extending the sign bit.
EXTU B 0 (<bits 15 to 8> of <Rd>)
Converts byte data in a general register to word data by
padding with zero bits.
TST B/W (EAd) – 0
Compares general register or memory contents with 0.
NEG B/W 0 – (EAd) (EAd)
Obtains the two’s complement of general register or
memory contents.
CLR B/W 0 (EAd)
Clears general register or memory contents to 0.
TAS B (EAd) — 0, (1)
2 (<bit 7> of <EAd>)
Tests general register or memory contents, then sets the
most significant bit (bit 7) to “1.
Note: B—byte; W—word
3.5.4 Logic Operations
Table 3-12 lists the four instructions that perform logic operations.
Table 3-12 Logic Operation Instructions
Instruction Size Function
Logical AND B/W Rd(EAs) Rd
operations Performs a logical AND operation on a general register
and another general register, memory, or immediate data.
OR B/W Rd(EAs) Rd
Performs a logical OR operation on a general register and
another general register, memory, or immediate data.
XOR B/W Rd(EAs) Rd
Performs a logical exclusive OR operation on a general register
and another general register, memory, or immediate data.
NOT B/W ¬ (EAd) (EAd)
Obtains the one’s complement of general register or memory
contents.
Note: B—byte; W—word
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Hitachi H8/500 Series Specifications

General IconGeneral
BrandHitachi
ModelH8/500 Series
CategoryComputer Hardware
LanguageEnglish

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