60 Description TM9100 Service Manual
© Tait Electronics Limited August 2005
Power Control
The steady-state power output of the transmitter is regulated using a
hardware control loop. With the 50W/40W radio, the sum of the forward
power output from the RF power amplifier and reverse power reflected from
the load is sensed by the directional coupler and fed back to the power
control loop. With the 25W radio, the forward power output from the RF
power amplifier is sensed by the directional coupler and fed back to the
power control loop. The PA output power is controlled by varying driver
gate bias voltage that has a calibrated maximum limit to prevent overdrive.
The power control signal is supplied by a 13-bit DAC driven by custom
logic.
Ramping Power ramp-up consists of two stages:
â– bias
â– power ramping
The timing between these two stages is carefully controlled in order to
achieve the correct overall wave shape and meet transient ACP
specifications. A typical ramping waveform is shown in Figure 2.14.
The timing between these two stages is critical to achieving the correct
overall wave shape in order to meet the specification for transient ACP
(adjacent channel power).
Bias Ramp-Up The steady-state final-stage bias level is supplied by an 8-bit DAC
programmed prior to ramp-up but held to zero by a switch on the DAC
output under the control of a
TX INHIBIT signal. Bias ramp-up begins upon
release by the
TX INHIBIT signal with the ramping shape being determined by
a low-pass filter. Owing to power leakage through the PA chain, ramping
the bias takes the PA output power from less than –20dBm for the
50W/40W or –10dBm for the 25W radio to approximately 25dB below
steady-state power.
Power Ramp-Up The power ramp signal is supplied by a 13-bit DAC that is controlled by
custom logic. The ramp is generated using a look-up table in custom logic
Figure 2.14 Typical ramping waveforms
Power
ramp
High power
powerLow
Power
Time
Bias
ramp
Bias
ramp
Power
ramp
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