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TM9100 Service Manual Circuit Descriptions 75

3.4 Frequency Control Loop

Introduction The FCL is included in the block diagram of the frequency synthesizer

(see Figure 3.4).

The FCL forms part of the frequency-synthesizer module. The basis of the

FCL is a VCXO, which generates the reference frequency required by the

main PLL of the synthesizer.

Elements of

FCL Circuitry

The FCL is a simple frequency-locked loop. The circuitry consists of the

following elements:

■ VCXO (XL501, Q501, Q503)

■ TCXO (XL500)

■ buffer amplifier (IC500)

■ mixer (IC501)

■ low-pass filter (IC502, pins 5 to 7)

■ modulator buffer amplifier (IC502, pins 1 to 3)

The TCXO supplies a reference frequency of 13.0000MHz, which is

extremely stable, regardless of the temperature. The VCXO runs at a

nominal frequency of 13.0000MHz, and is frequency-locked to the TCXO

reference frequency.

Circuit Operation The VCXO output is mixed with the TCXO output to create a nominal

difference (or offset) frequency

SYN CDC FCL of 12.0kHz. The signal SYN CDC

FCL is fed via the CODEC IC502 in the CODEC circuitry to the FPGA on

the digital board. The FPGA detects the offset frequency, compares it with

the programmed offset frequency, and outputs a corresponding feedback

signal

CDC VCXO MOD via IC205. The feedback signal is amplified and inverted

by the modulator buffer amplifier and output as the loop voltage for the

VCXO. With this design the VCXO frequency can be adjusted by very

small precise amounts, and because the loop is locked, the VCXO inherits

the temperature stability of the TCXO.

Modulation The FCL modulation is implemented within the FPGA and appears at the

output of IC205, and therefore on the VCXO loop voltage. Consequently,

the VCXO is frequency modulated directly by the relevant modulation

information. The latter may be the microphone audio, an audio tap-in

signal, internal modem signals, or any combination of these.

Tait TM9100 Service Manual

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