2-Port OC-48c/STM-16 POS SPA Architecture
The following figure identifies the primary hardware devices that are part of the 2-Port OC-48c/STM-16 POS
SPA architecture.
Figure 7: 2-Port OC-48c/STM-16 POS SPA Architecture
Path of a Packet in the Ingress Direction
The following steps describe the path of an ingress packet through the 2-Port OC-48c/STM-16 POS SPA:
1
The framer receives SONET/SDH streams from the SFP optics, extracts clocking and data, and processes
the section, line, and path overhead.
2
The framer detects Loss of Signal (LOS), Loss of Frame (LOF), Severely Errored Frame (SEF), Line
Alarm Indication Signal (AIS-L), Loss of Pointer (LOP), Line Remote Defect Indication Signal (Enhanced
RDI-L), Path Alarm Indication Signal (AIS-P), Standard and Enhanced Path Remote Defect Indication
Signal (RDI-P), Path Remote Error Indication (Enhanced REI-P). The framer extracts or inserts DCC
bytes.
3
The framer processes the S1 synchronization status byte, the pointer action bytes (per Telcordia
GR-253-CORE), and extracts or inserts DCC bytes.
4
The POS processor extracts the POS frame payload and verifies the frame size and frame check sequence
(FCS).
5
The POS processor supports PPP, Frame Relay, or HDLC modes and optionally performs payload
scrambling.
6
The POS processor passes valid frames to the System Packet Level Interface 4.2 (SPI4.2) interface on the
SPA.
7
The SPI4.2 interface transfers frames to the host through the SPI4.2 bus for further processing and switching.
Path of a Packet in the Egress Direction
The following steps describe the path of an egress packet through the 2-Port OC-48c/STM-16 POS SPA:
1
The host sends packets to the SPA using the SPI4.2 bus.
2
The SPA stores the data in the appropriate SPI4 channel’s first-in first-out (FIFO) queue.
Cisco ASR 1000 Series Aggregation Services Routers SIP and SPA Software Configuration Guide, Cisco IOS
XE Everest 16.5
190 OL-14127-17
Overview of the POS SPAs
2-Port OC-48c/STM-16 POS SPA Architecture
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