LCD Controller
18-8
MPC823e REFERENCE MANUAL
MOTOROLA
LCD CONTROLLER
18
18.3 LCD CONTROLLER OPERATION
The LCD controller uses the system interface unit to communicate with the core and external
system. It has its own DMA functionality to fetch display memory into the FIFOs for pixel
generation. The LCDCLK signal is derived from the SPLL output (VCOOUT) and is fed to
the timing generator for vertical, horizontal, and frame timing. The register set is used to
program the timing parameters for an LCD panel. Figure 18-7 illustrates the various
modules of the LCD controller.
Figure 18-7. LCD Functional Module
FIFOA
FIFOB
PIXEL
HORIZONTAL CONTROL
VERTICAL CONTROL
REGISTERS
VCOOUT CLOCK
DMA CONTROLLER
TIMING GENERATOR
FRAME CONTROL
GENERATION
DFLCD DFALCD
SYSTEM INTERFACE UNIT
EOF IRQ
LCD INTERFACE
SHIFT/CLK
LCD_AC/LOE
FRAME/VSYNC
LOAD/HSYNC
LD[0:8]
LCD_A
LCD_B
LCD_C
LCDCLK
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