Memory Management Unit
MOTOROLA
MPC823e REFERENCE MANUAL
11-3
MEMORY MANAGEMENT
11
UNIT
A successful TLB hit occurs if the incoming effective address matches the EPN stored in a
valid TLB entry and the CASID value stored in the M_CASID
register matches the entry’s
ASID field. At the same time, the subpage validity flag is set for the subpage pointed to by
the incoming effective address. If a hit is detected, the content of the real page number is
concatenated with the appropriate number of least-significant bits from the effective address
to form the real address that is then sent to the cache and memory system.
11.3 PROTECTION
Access control is assigned on a page-by-page basis and any further manipulation is
conducted on a group basis.
Figure 11-1. Block Diagram of Effective-to-Real Address Translation For 4K Pages
ENABLED
TRANSLATION LOOKASIDE BUFFER
32-BIT REAL ADDRESS
BYTE
12
20
PAGE
NO ACCESS
FREE ACCESS
EXCEPTION
PAGE PROTECTION
TRANSLATION
MSRPR
IMPLEMENTATION SPECIFIC
TLB MISS INTERRUPTS
TO CORE
IMPLEMENTATION
SPECIFIC
ERROR INTERRUPTS
TO CORE
LOGIC
PROTECTION
GROUP NUMBER
32-BIT LOGICAL
ADDRESS
PROTECTION
LOOKUP
TABLE
20
BYTE
REAL PAGE NUMBER
20
12
32-BIT EFFECTIVE
ADDRESS
CASID
(FROM M_CASID)
TRANSLATION
ENABLED
32-ENTRY FULLY ASSOCIATIVE ARRAY
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